| Commit message (Expand) | Author | Age | Files | Lines |
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| ... | |
| * | target-mips: add msa_reset(), global msa register | Yongbok Kim | 2014-11-03 | 1 | -0/+56 |
| * | target-mips: add MSA opcode enum | Yongbok Kim | 2014-11-03 | 1 | -0/+245 |
| * | target-mips: stop translation after ctc1 | Yongbok Kim | 2014-11-03 | 1 | -0/+6 |
| * | target-mips: correctly handle access to unimplemented CP0 register | Leon Alrae | 2014-11-03 | 1 | -278/+260 |
| * | target-mips: implement forbidden slot | Leon Alrae | 2014-11-03 | 1 | -35/+74 |
| * | target-mips: add Config5.SBRI | Leon Alrae | 2014-11-03 | 1 | -1/+23 |
| * | target-mips: add BadInstr and BadInstrP support | Leon Alrae | 2014-11-03 | 1 | -6/+70 |
| * | target-mips: add TLBINV support | Leon Alrae | 2014-11-03 | 1 | -0/+22 |
| * | target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1} | Leon Alrae | 2014-11-03 | 1 | -2/+24 |
| * | target-mips: add KScratch registers | Leon Alrae | 2014-11-03 | 1 | -0/+44 |
| * | target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX | Peter Maydell | 2014-10-14 | 1 | -19/+1 |
| * | target-mips/translate.c: Add ifdef guard around check_mips64() | Peter Maydell | 2014-10-14 | 1 | -0/+2 |
| * | target-mips: fix broken MIPS16 and microMIPS | Yongbok Kim | 2014-10-14 | 1 | -182/+116 |
| * | target-mips/translate.c: Update OPC_SYNCI | Dongxue Zhang | 2014-10-14 | 1 | -1/+6 |
| * | target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions | Yongbok Kim | 2014-10-14 | 1 | -2/+16 |
| * | target-mips: do not allow Status.FR=0 mode in 64-bit FPU | Leon Alrae | 2014-10-14 | 1 | -0/+6 |
| * | target-mips: add new Floating Point Comparison instructions | Yongbok Kim | 2014-10-14 | 1 | -2/+204 |
| * | target-mips: add new Floating Point instructions | Leon Alrae | 2014-10-14 | 1 | -44/+397 |
| * | target-mips: add AUI, LSA and PCREL instruction families | Leon Alrae | 2014-10-14 | 1 | -14/+189 |
| * | target-mips: add compact and CP1 branches | Yongbok Kim | 2014-10-13 | 1 | -14/+459 |
| * | target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions | Yongbok Kim | 2014-10-13 | 1 | -12/+108 |
| * | target-mips: Status.UX/SX/KX enable 32-bit address wrapping | Leon Alrae | 2014-10-13 | 1 | -5/+1 |
| * | target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6 | Leon Alrae | 2014-10-13 | 1 | -59/+62 |
| * | target-mips: redefine Integer Multiply and Divide instructions | Leon Alrae | 2014-10-13 | 1 | -21/+322 |
| * | target-mips: move PREF, CACHE, LLD and SCD instructions | Leon Alrae | 2014-10-13 | 1 | -1/+28 |
| * | target-mips: signal RI Exception on DSP and Loongson instructions | Leon Alrae | 2014-10-13 | 1 | -97/+98 |
| * | target-mips: split decode_opc_special* into *_r6 and *_legacy | Leon Alrae | 2014-10-13 | 1 | -68/+160 |
| * | target-mips: extract decode_opc_special* from decode_opc | Leon Alrae | 2014-10-13 | 1 | -805/+845 |
| * | target-mips: move LL and SC instructions | Leon Alrae | 2014-10-13 | 1 | -2/+26 |
| * | target-mips: add SELEQZ and SELNEZ instructions | Leon Alrae | 2014-10-13 | 1 | -2/+16 |
| * | target-mips: signal RI Exception on instructions removed in R6 | Leon Alrae | 2014-10-13 | 1 | -8/+56 |
| * | trace: [tcg] Include TCG-tracing header on all targets | Lluís Vilanova | 2014-08-12 | 1 | -0/+3 |
| * | target-mips/translate.c: Free TCG in OPC_DINSV | Dongxue Zhang | 2014-07-28 | 1 | -0/+3 |
| * | mips/kvm: Init EBase to correct KSEG0 | James Hogan | 2014-07-05 | 1 | -1/+7 |
| * | target-mips: copy CP0_Config1 into DisasContext | Aurelien Jarno | 2014-06-20 | 1 | -9/+11 |
| * | Merge remote-tracking branch 'remotes/kvm/uq/master' into staging | Peter Maydell | 2014-06-20 | 1 | -0/+2 |
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| | * | target-mips: Reset CPU timer consistently | James Hogan | 2014-06-18 | 1 | -0/+2 |
| * | | target-mips: implement UserLocal Register | Petar Jovanovic | 2014-06-18 | 1 | -3/+52 |
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| * | softmmu: introduce cpu_ldst.h | Paolo Bonzini | 2014-06-05 | 1 | -0/+1 |
| * | tcg: Invert the inclusion of helper.h | Richard Henderson | 2014-05-28 | 1 | -3/+2 |
| * | target-mips: fix MTHC1 and MFHC1 when FPU in FR=0 mode | Petar Jovanovic | 2014-03-25 | 1 | -35/+44 |
| * | cpu: Move breakpoints field from CPU_COMMON to CPUState | Andreas Färber | 2014-03-13 | 1 | -2/+2 |
| * | cpu: Move exception_index field from CPU_COMMON to CPUState | Andreas Färber | 2014-03-13 | 1 | -3/+1 |
| * | target-mips: add user-mode FR switch support for MIPS32r5 | Petar Jovanovic | 2014-02-10 | 1 | -2/+12 |
| * | target-mips: add support for CP0_Config5 | Petar Jovanovic | 2014-02-10 | 1 | -2/+12 |
| * | target-mips: add support for CP0_Config4 | Petar Jovanovic | 2014-02-10 | 1 | -2/+13 |
| * | target-mips: Use new qemu_ld/st opcodes | Aurelien Jarno | 2013-12-21 | 1 | -67/+52 |
| * | target-mips: fix 64-bit FPU config for user-mode emulation | Petar Jovanovic | 2013-12-09 | 1 | -2/+5 |
| * | Merge remote-tracking branch 'rth/tcg-pull' into staging | Anthony Liguori | 2013-10-11 | 1 | -4/+0 |
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| | * | tcg: Move helper registration into tcg_context_init | Richard Henderson | 2013-10-10 | 1 | -4/+0 |
