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path: root/target-mips/translate.c
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* target-mips: fix multiple TCG registers covering same dataYongbok Kim2014-11-071-5/+3
* mips: Ensure PC update with MTC0 single-steppingMaciej W. Rozycki2014-11-071-1/+1
* target-mips: fix for missing delay slot in BC1EQZ and BC1NEZLeon Alrae2014-11-071-0/+1
* mips: Respect CP0.Status.CU1 for microMIPS FP branchesMaciej W. Rozycki2014-11-071-2/+7
* target-mips: add MSA MI10 format instructionsYongbok Kim2014-11-031-1/+48
* target-mips: add MSA 2RF format instructionsYongbok Kim2014-11-031-0/+74
* target-mips: add MSA VEC/2R format instructionsYongbok Kim2014-11-031-0/+113
* target-mips: add MSA 3RF format instructionsYongbok Kim2014-11-031-0/+163
* target-mips: add MSA ELM format instructionsYongbok Kim2014-11-031-0/+118
* target-mips: add MSA 3R format instructionsYongbok Kim2014-11-031-0/+242
* target-mips: add MSA BIT format instructionsYongbok Kim2014-11-031-0/+88
* target-mips: add MSA I5 format instructionYongbok Kim2014-11-031-0/+77
* target-mips: add MSA I8 format instructionsYongbok Kim2014-11-031-2/+80
* target-mips: add MSA branch instructionsYongbok Kim2014-11-031-114/+220
* target-mips: add msa_reset(), global msa registerYongbok Kim2014-11-031-0/+56
* target-mips: add MSA opcode enumYongbok Kim2014-11-031-0/+245
* target-mips: stop translation after ctc1Yongbok Kim2014-11-031-0/+6
* target-mips: correctly handle access to unimplemented CP0 registerLeon Alrae2014-11-031-278/+260
* target-mips: implement forbidden slotLeon Alrae2014-11-031-35/+74
* target-mips: add Config5.SBRILeon Alrae2014-11-031-1/+23
* target-mips: add BadInstr and BadInstrP supportLeon Alrae2014-11-031-6/+70
* target-mips: add TLBINV supportLeon Alrae2014-11-031-0/+22
* target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae2014-11-031-2/+24
* target-mips: add KScratch registersLeon Alrae2014-11-031-0/+44
* target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACXPeter Maydell2014-10-141-19/+1
* target-mips/translate.c: Add ifdef guard around check_mips64()Peter Maydell2014-10-141-0/+2
* target-mips: fix broken MIPS16 and microMIPSYongbok Kim2014-10-141-182/+116
* target-mips/translate.c: Update OPC_SYNCIDongxue Zhang2014-10-141-1/+6
* target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructionsYongbok Kim2014-10-141-2/+16
* target-mips: do not allow Status.FR=0 mode in 64-bit FPULeon Alrae2014-10-141-0/+6
* target-mips: add new Floating Point Comparison instructionsYongbok Kim2014-10-141-2/+204
* target-mips: add new Floating Point instructionsLeon Alrae2014-10-141-44/+397
* target-mips: add AUI, LSA and PCREL instruction familiesLeon Alrae2014-10-141-14/+189
* target-mips: add compact and CP1 branchesYongbok Kim2014-10-131-14/+459
* target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructionsYongbok Kim2014-10-131-12/+108
* target-mips: Status.UX/SX/KX enable 32-bit address wrappingLeon Alrae2014-10-131-5/+1
* target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6Leon Alrae2014-10-131-59/+62
* target-mips: redefine Integer Multiply and Divide instructionsLeon Alrae2014-10-131-21/+322
* target-mips: move PREF, CACHE, LLD and SCD instructionsLeon Alrae2014-10-131-1/+28
* target-mips: signal RI Exception on DSP and Loongson instructionsLeon Alrae2014-10-131-97/+98
* target-mips: split decode_opc_special* into *_r6 and *_legacyLeon Alrae2014-10-131-68/+160
* target-mips: extract decode_opc_special* from decode_opcLeon Alrae2014-10-131-805/+845
* target-mips: move LL and SC instructionsLeon Alrae2014-10-131-2/+26
* target-mips: add SELEQZ and SELNEZ instructionsLeon Alrae2014-10-131-2/+16
* target-mips: signal RI Exception on instructions removed in R6Leon Alrae2014-10-131-8/+56
* trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova2014-08-121-0/+3
* target-mips/translate.c: Free TCG in OPC_DINSVDongxue Zhang2014-07-281-0/+3
* mips/kvm: Init EBase to correct KSEG0James Hogan2014-07-051-1/+7
* target-mips: copy CP0_Config1 into DisasContextAurelien Jarno2014-06-201-9/+11
* Merge remote-tracking branch 'remotes/kvm/uq/master' into stagingPeter Maydell2014-06-201-0/+2
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