hqemu - HQEMU

	Commit message (Expand)	Author	Age	Files	Lines
*	target-mips: remove POOL48A from the microMIPS decoding	Aurelien Jarno	2012-11-24	1	-1/+0
*	target-mips: Clean up microMIPS32 major opcode	陳韋任 (Wei-Ren Chen)	2012-11-24	1	-7/+17
*	target-mips: Add comments on POOL32Axf encoding	陳韋任 (Wei-Ren Chen)	2012-11-24	1	-0/+17
*	TCG: Use gen_opc_buf from context instead of global variable.	Evgeny Voevodin	2012-11-17	1	-3/+3
*	TCG: Use gen_opc_ptr from context instead of global variable.	Evgeny Voevodin	2012-11-17	1	-4/+5
*	target-mips: fix wrong microMIPS opcode encoding	陳韋任 (Wei-Ren Chen)	2012-11-15	1	-1/+1
*	target-mips: Fix seg fault for LUI when MIPS_DEBUG_DISAS==1.	Eric Johnson	2012-11-11	1	-7/+11
*	disas: avoid using cpu_single_env	Blue Swirl	2012-11-10	1	-1/+1
*	target-mips: use deposit instead of hardcoded version	Aurelien Jarno	2012-10-31	1	-28/+4
*	target-mips: optimize ddiv/ddivu/div/divu with movcond	Aurelien Jarno	2012-10-31	1	-48/+37
*	target-mips: implement movn/movz using movcond	Aurelien Jarno	2012-10-31	1	-15/+12
*	target-mips: don't use local temps for store conditional	Aurelien Jarno	2012-10-31	1	-5/+6
*	target-mips: implement unaligned loads using TCG	Aurelien Jarno	2012-10-31	1	-13/+62
*	target-mips: optimize load operations	Aurelien Jarno	2012-10-31	1	-4/+12
*	target-mips: cleanup load/store operations	Aurelien Jarno	2012-10-31	1	-64/+35
*	target-mips: use the softfloat floatXX_muladd functions	Aurelien Jarno	2012-10-31	1	-12/+12
*	target-mips: do not save CPU state when using retranslation	Aurelien Jarno	2012-10-31	1	-20/+0
*	target-mips: correctly restore btarget upon exception	Aurelien Jarno	2012-10-31	1	-0/+11
*	target-mips: remove #if defined(TARGET_MIPS64) in opcode enums	Aurelien Jarno	2012-10-31	1	-36/+0
*	target-mips: Add ASE DSP accumulator instructions	Jia Liu	2012-10-31	1	-0/+351
*	target-mips: Add ASE DSP compare-pick instructions	Jia Liu	2012-10-31	1	-0/+350
*	target-mips: Add ASE DSP bit/manipulation instructions	Jia Liu	2012-10-31	1	-0/+249
*	target-mips: Add ASE DSP multiply instructions	Jia Liu	2012-10-31	1	-0/+485
*	target-mips: Add ASE DSP GPR-based shift instructions	Jia Liu	2012-10-31	1	-0/+324
*	target-mips: Add ASE DSP arithmetic instructions	Jia Liu	2012-10-31	1	-3/+792
*	target-mips: Add ASE DSP load instructions	Jia Liu	2012-10-31	1	-0/+88
*	target-mips: Add ASE DSP branch instructions	Jia Liu	2012-10-31	1	-0/+36
*	Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number	Jia Liu	2012-10-31	1	-27/+95
*	target-mips: Add ASE DSP resources access check	Jia Liu	2012-10-31	1	-0/+23
*	target-mips: Use TCG registers for the FPU.	Richard Henderson	2012-10-28	1	-42/+54
*	Emit debug_insn for CPU_LOG_TB_OP_OPT as well.	Richard Henderson	2012-09-27	1	-1/+2
*	target-mips: Implement Loongson Multimedia Instructions	Richard Henderson	2012-09-19	1	-3/+376
*	target-mips: Always evaluate debugging macro arguments	Richard Henderson	2012-09-19	1	-14/+17
*	target-mips: Fix MIPS_DEBUG.	Richard Henderson	2012-09-19	1	-36/+38
*	target-mips: Set opn in gen_ldst_multiple.	Richard Henderson	2012-09-19	1	-0/+6
*	target-mips: switch to AREG0 free mode	Blue Swirl	2012-09-15	1	-368/+386
*	MIPS/user: Fix reset CPU state initialization	Maciej W. Rozycki	2012-09-08	1	-13/+3
*	target-mips: allow microMIPS SWP and SDP to have RD equal to BASE	Eric Johnson	2012-08-27	1	-1/+9
*	target-mips: add privilege level check to several Cop0 instructions	Eric Johnson	2012-08-27	1	-0/+9
*	mips-linux-user: Always support rdhwr.	Richard Henderson	2012-08-27	1	-0/+4
*	target-mips: Streamline indexed cp1 memory addressing.	Richard Henderson	2012-08-27	1	-2/+1
*	Fix order of CVT.PS.S operands	Richard Sandiford	2012-08-27	1	-1/+1
*	Fix operands of RECIP2.S and RECIP2.PS	Richard Sandiford	2012-08-27	1	-2/+2
*	target-mips: Enable access to required RDHWR hardware registers	Meador Inge	2012-08-23	1	-2/+3
*	MIPS: Correct FCR0 initialization	Nathan Froyd	2012-08-09	1	-0/+1
*	target-mips: Let cpu_mips_init() return MIPSCPU	Andreas Färber	2012-06-04	1	-2/+2
*	target-mips: Use cpu_reset() in cpu_mips_init()	Andreas Färber	2012-06-04	1	-1/+1
*	mips: Fix BC1ANY[24]F instructions	Richard Sandiford	2012-05-19	1	-4/+4
*	target-mips: Start QOM'ifying CPU init	Andreas Färber	2012-04-30	1	-1/+0
*	target-mips: QOM'ify CPU	Andreas Färber	2012-04-30	1	-1/+3