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* target-mips: allow microMIPS SWP and SDP to have RD equal to BASEEric Johnson2012-08-271-1/+9
| | | | | | | | | | The microMIPS SWP and SDP instructions do not modify GPRs. So their behavior is well defined when RD equals BASE. The MIPS Architecture Verification Programs (AVPs) check that they work as expected. This is required for AVPs to pass. Signed-off-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: add privilege level check to several Cop0 instructionsEric Johnson2012-08-271-0/+9
| | | | | | | | | The MIPS Architecture Verification Programs (AVPs) check privileged instructions for the required privilege level. These changes are needed to pass the AVP suite. Signed-off-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* mips-linux-user: Always support rdhwr.Richard Henderson2012-08-271-0/+4
| | | | | | | | | | The kernel will emulate this instruction if it's not supported natively. This insn is used for TLS, among other things, and so is required by modern glibc. Signed-off-by: Richard Henderson <rth@twiddle.net> Cc: Riku Voipio <riku.voipio@iki.fi> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Streamline indexed cp1 memory addressing.Richard Henderson2012-08-271-2/+1
| | | | | | We've already eliminated both base and index being zero. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Fix order of CVT.PS.S operandsRichard Sandiford2012-08-271-1/+1
| | | | | | | | | The FS input to CVT.PS.S is the high half and FT is the low half. tcg_gen_concat_i32_i64 takes the low half first, so the operands were in the wrong order. Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Fix operands of RECIP2.S and RECIP2.PSRichard Sandiford2012-08-271-2/+2
| | | | | | | | Read the second input operand of RECIP2.S and RECIP2.PS from FT rather than FD. RECIP2.D is already correct. Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Enable access to required RDHWR hardware registersMeador Inge2012-08-231-2/+3
| | | | | | | | | | | | | | | | | While running in the usermode emulator all of the required* MIPS32r2 RDHWR hardware registers should be accessible (the Linux kernel enables access to these same registers). Note that these registers are still enabled when the MIPS ISA is not release 2. This is OK since the Linux kernel emulates access to them when they are not available in hardware. * There is also the ULR register which is only recommended for full release 2 compliance. Incidentally, accessing this register in the current implementation works fine without flipping its access bit. Signed-off-by: Meador Inge <meadori@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* MIPS: Correct FCR0 initializationNathan Froyd2012-08-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change addresses a problem where QEMU incorrectly traps on floating-point MADD group instructions with SIGILL, at least while emulating MIPS32r2 processors. These instructions use the COP1X major opcode and include ones like: madd.d $f2,$f4,$f2,$f6 Here's Nathan's original analysis of the problem: "QEMU essentially does: d = find_cpu (cpu_string) // get CPU definition fpu_init (env, d) // initialize fpu state (init FCR0, basically) cpu_reset (env) ...and the cpu_reset call clears all interesting state that fpu_init setup, then proceeds to reinitialize all the CP0 registers...but not FCR0." I have verified this change with system emulation running the GDB test suite for the mips-sde-elf target (o32, big endian, 24Kf CPU emulated), there were 55 progressions and no regressions. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-mips: Let cpu_mips_init() return MIPSCPUAndreas Färber2012-06-041-2/+2
| | | | | | | Turn cpu_init macro into a static inline function returning CPUMIPSState for backwards compatibility. Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-mips: Use cpu_reset() in cpu_mips_init()Andreas Färber2012-06-041-1/+1
| | | | | | | | | | | | | | Commit 0f71a7095db6bc055bc5bb520d85ea650cca8a33 (target-mips: QOM'ify CPU) hooked up cpu_state_reset() to CPUClass::reset(). Dropping the introduction of subclasses for 1.1, due to mips_def_t the reset code could not be QOM'ified yet, i.e. cpu_state_reset() will not forward to CPUClass::reset(). Update cpu_mips_init() with cpu_reset() nontheless, indirectly calling cpu_state_reset(), so that generic code can be converted to call cpu_reset(). Signed-off-by: Andreas Färber <afaerber@suse.de>
* mips: Fix BC1ANY[24]F instructionsRichard Sandiford2012-05-191-4/+4
| | | | | | | | | | | | There's some dodgy application of De Morgan's law in the emulation of the MIPS BC1ANY[24]F instructions: they end up branching only if all CCs are false, rather than if one CC is. Tested on mips64-linux-gnu, where it fixes the GCC MIPS3D tests. Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-mips: Start QOM'ifying CPU initAndreas Färber2012-04-301-1/+0
| | | | | | | | Move code not dependent on mips_def_t from cpu_mips_init() into a QOM initfn, as a start. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-mips: QOM'ify CPUAndreas Färber2012-04-301-1/+3
| | | | | | | | | Embed CPUMIPSState as first member of QOM MIPSCPU. Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-mips: Don't overuse CPUStateAndreas Färber2012-03-141-178/+178
| | | | | | | | | Scripted conversion: sed -i "s/CPUState/CPUMIPSState/g" target-mips/*.[hc] sed -i "s/#define CPUMIPSState/#define CPUState/" target-mips/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
* Rename cpu_reset() to cpu_state_reset()Andreas Färber2012-03-141-2/+2
| | | | | | | | | | Frees the identifier cpu_reset for QOM CPUs (manual rename). Don't hide the parameter type behind explicit casts, use static functions with strongly typed argument to indirect. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
* target-mips: Clean includesStefan Weil2012-02-281-7/+0
| | | | | | | Remove some include statements which are not needed. Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <sw@weilnetz.de>
* mips: Initialize MT state at resetEdgar E. Iglesias2011-09-061-0/+26
| | | | | | | Only TC0 on VPE0 is active after reset. All other VPEs and TCs start in sleep. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* mips: Hook in more reg accesses via mttr/mftrEdgar E. Iglesias2011-09-061-0/+86
| | | | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* Use glib memory allocation and free functionsAnthony Liguori2011-08-201-1/+1
| | | | | | qemu_malloc/qemu_free no longer exist after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Remove exec-all.h include directivesBlue Swirl2011-06-261-1/+0
| | | | | | Most exec-all.h include directives are now useless, remove them. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Remove unused function parameters from gen_pc_load and rename the functionStefan Weil2011-04-201-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Function gen_pc_load was introduced in commit d2856f1ad4c259e5766847c49acbb4e390731bd4. The only reason for parameter searched_pc was a debug statement in target-i386/translate.c. Parameter puc was needed by target-sparc until commit d7da2a10402f1644128b66414ca8f86bdea9ae7c. Remove searched_pc from the debug statement and remove both parameters from the parameter list of gen_pc_load. As the function name gen_pc_load was also misleading, it is now called restore_state_to_opc. This new name was suggested by Peter Maydell, thanks. v2: Remove last parameter, too, and rename the function. v3: Fix [] typo in target-arm/translate.c. Fix wrong SHA1 object name in commit message (copy+paste error). Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
* Fix conversions from pointer to tcg_target_longStefan Weil2011-04-101-1/+1
| | | | | | | | | | | | tcg_gen_exit_tb takes a parameter of type tcg_target_long, so the type casts of pointer to long should be replaced by type casts of pointer to tcg_target_long (suggested by Blue Swirl). These changes are needed for build environments where sizeof(long) != sizeof(void *), especially for w64. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: fix save_cpu_state() callsAurelien Jarno2011-01-241-6/+6
| | | | | | | | | | The rule is: - don't save PC if the exception is only triggered by softmmu. - save PC if the exception can be triggered by an helper. Fix a 64-bit kernel crash when loading modules. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* mips: Break TBs after mfc0_countEdgar E. Iglesias2011-01-181-2/+6
| | | | | | | | Break the TB after reading the count register. This makes it possible to take timer interrupts immediately after a read of a possibly expired timer. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* target-mips: fix translation of MT instructionsNathan Froyd2010-12-221-4/+4
| | | | | | | | | | | | | | | | The translation of dmt/emt/dvpe/evpe was doing the moral equivalent of: int x; ... /* no initialization of x */ x = f (x); which confused later bits of TCG rather badly, leading to crashes. Fix the helpers to only return results (those instructions have no inputs), and fix the translation code accordingly. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-xxx: Use fprintf_function (format checking)Stefan Weil2010-10-301-7/+5
| | | | | | | | | | | | | fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* mips: avoid write only variablesBlue Swirl2010-10-131-0/+29
| | | | | | | | | | Compiling with GCC 4.6.0 20100925 produced a lot of warnings like: /src/qemu/target-mips/translate.c: In function 'gen_ld': /src/qemu/target-mips/translate.c:1039:17: error: variable 'opn' set but not used [-Werror=unused-but-set-variable] Fix by adding a dummy cast so that the variable is not unused. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Correctly identify multiple cpus in SMP systemsHervé Poussineau2010-07-311-2/+1
| | | | | Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* mips: more fixes to the MIPS interrupt glue logicAurelien Jarno2010-07-251-2/+10
| | | | | | | | | | Commit 36388314febad3d7675ab919287f03733a560ff6 moved most of the interrupt logic to cpu-exec.c. Remove the remaining useless code and fix software interrupts. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Edgar E. Iglesias <edgar@axis.com> Tested-by: Edgar E. Iglesias <edgar@axis.com>
* target-mips: add loongson 2E & 2F integer instructionsAurelien Jarno2010-07-111-0/+271
| | | | | | | This patch adds support for loongson 2E & 2F instructions. They are the same instructions, but differ by the opcode encoding. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: add Loongson support prefetchAurelien Jarno2010-07-011-35/+43
| | | | | | | Loongson CPU uses a load to zero register for prefetch. Emulate it as a NOP. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: split load and storeAurelien Jarno2010-07-011-155/+183
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: fix DINSU instructionAurelien Jarno2010-06-301-1/+1
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: enable movn/movz on loongson 2E & 2FAurelien Jarno2010-06-291-1/+2
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Fix compilationStefan Weil2010-06-091-1/+1
| | | | | | | | | TCGv t1 needs tcg_temp_free instead of tcg_temp_free_i32. Cc: Nathan Froyd <froydnj@codesourcery.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: microMIPS ASE supportNathan Froyd2010-06-091-5/+2385
| | | | | | | | Add instruction decoding for the microMIPS ASE. All we do is decode and then forward to the existing gen_* routines. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: mips16 cleanupsNathan Froyd2010-06-091-7/+17
| | | | | | | | | | | Change code handling mips16-specific branches to use ISA-neutral special opcodes. Since there are several places where the delay slot requirements for microMIPS branches differ from mips16 branches, using opcodes is easier than checking hflags, then checking mips16 vs. microMIPS. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: refactor c{, abs}.cond.fmt insnsNathan Froyd2010-06-091-83/+81
| | | | | | | | Move all knowledge about coprocessor-checking and register numbering into the gen_cmp* helper functions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: move FP FMT comments closer to the definitionsAurelien Jarno2010-06-091-14/+14
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: define constants for magic numbersNathan Froyd2010-06-091-142/+295
| | | | | | | | | Add FMT_* constants for the floating-point format field in opcodes and tweak a few places to use them. Add enums for various invocations of FOP and tweak gen_farith and its lone caller accordingly. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: break out [ls][wd]c1 and rdhwr insn generationNathan Froyd2010-06-081-47/+59
| | | | | | Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Remove duplicate CPU log.Richard Henderson2010-05-051-6/+0
| | | | | | | Logging for -d cpu is done in generic code. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Fix format specifiers for fpu_fprintfStefan Weil2010-04-091-14/+20
| | | | | | | | | | | In the previous patch which introduced fprintf_function to allow parameter checking by gcc some compiler warnings remained unfixed. These warnings are fixed here. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Fix one more format specifier for cpu_fprintfStefan Weil2010-04-081-1/+3
| | | | | | | env->bcond must be printed using TARGET_FMT_ld. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* remove TARGET_* defines from translate-all.cPaolo Bonzini2010-04-081-0/+2
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: use newer logical opsAurelien Jarno2010-03-041-8/+4
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: use setcond when possibleAurelien Jarno2010-03-021-77/+20
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: fix ROTR and DROTR by zeroNathan Froyd2010-02-231-0/+4
| | | | | Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: fix CpU exception for coprocessor 0Nathan Froyd2010-02-231-1/+1
| | | | | | | | When we signal a CpU exception for coprocessor 0, we should indicate that it's for coprocessor 0 instead of coprocessor 1. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: remove useless sign extensionAurelien Jarno2010-02-231-2/+0
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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