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path: root/target-mips/op_helper.c
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* target-mips: ll and lld cause AdEL exception for unaligned addressLeon Alrae2015-02-131-3/+7
* target-mips: Don't use _raw load/store accessorsPeter Maydell2015-01-201-2/+2
* target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki2014-12-161-12/+0
* target-mips: Also apply the CP0.Status mask to MTTC0Maciej W. Rozycki2014-12-161-1/+2
* target-mips: Fix CP0.Config3.ISAOnExc write accessesMaciej W. Rozycki2014-12-161-0/+8
* target-mips: Correct the writes to Status and Cause registers via gdbstubMaciej W. Rozycki2014-12-161-84/+7
* target-mips: Correct the handling of writes to CP0.Status for MIPSr6Maciej W. Rozycki2014-12-161-2/+4
* target-mips: Restore the order of helpersMaciej W. Rozycki2014-12-161-159/+160
* target-mips: Remove unused `FLOAT_OP' macroMaciej W. Rozycki2014-12-161-2/+0
* target-mips: Make `helper_float_cvtw_s' consistent with the remaining helpersMaciej W. Rozycki2014-12-161-1/+1
* target-mips: add MSA MI10 format instructionsYongbok Kim2014-11-031-4/+80
* target-mips: remove duplicated mips/ieee mapping functionYongbok Kim2014-11-031-2/+2
* target-mips: add MSA defines and data structureYongbok Kim2014-11-031-0/+1
* target-mips: add restrictions for possible values in registersLeon Alrae2014-11-031-17/+53
* target-mips: add BadInstr and BadInstrP supportLeon Alrae2014-11-031-2/+15
* target-mips: add TLBINV supportLeon Alrae2014-11-031-7/+58
* target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae2014-11-031-3/+22
* target-mips: add RI and XI fields to TLB entryLeon Alrae2014-11-031-0/+8
* target-mips: add ULL suffix in bitswap to avoid compiler warningLeon Alrae2014-10-241-6/+6
* target-mips/op_helper.c: Remove unused do_lbu() functionPeter Maydell2014-10-141-1/+0
* target-mips: add new Floating Point Comparison instructionsYongbok Kim2014-10-141-0/+111
* target-mips: add new Floating Point instructionsLeon Alrae2014-10-141-0/+104
* target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructionsYongbok Kim2014-10-131-0/+23
* target-mips: Ignore unassigned accesses with KVMJames Hogan2014-08-071-0/+11
* target-mips: implement UserLocal RegisterPetar Jovanovic2014-06-181-1/+13
* softmmu: introduce cpu_ldst.hPaolo Bonzini2014-06-051-5/+1
* softmmu: commonize helper definitionsPaolo Bonzini2014-06-051-14/+0
* softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini2014-06-051-1/+0
* softmmu: make do_unaligned_access a method of CPUPaolo Bonzini2014-06-051-6/+5
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-281-1/+1
* target-mips: Avoid shifting left into sign bitPeter Maydell2014-03-271-1/+1
* cputlb: Change tlb_flush() argument to CPUStateAndreas Färber2014-03-131-1/+3
* exec: Change cpu_abort() argument to CPUStateAndreas Färber2014-03-131-2/+9
* translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber2014-03-131-1/+1
* cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber2014-03-131-2/+2
* exec: Change tlb_fill() argument to CPUStateAndreas Färber2014-03-131-3/+4
* cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-3/+6
* cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber2014-03-131-1/+2
* target-mips: add user-mode FR switch support for MIPS32r5Petar Jovanovic2014-02-101-3/+38
* target-mips: add support for CP0_Config5Petar Jovanovic2014-02-101-0/+6
* target-mips: add support for CP0_Config4Petar Jovanovic2014-02-101-0/+6
* cpu: Use QTAILQ for CPU listAndreas Färber2013-09-031-6/+4
* target-mips: Remove assignment to a variable which is never usedStefan Weil2013-07-291-1/+0
* cpu: Make first_cpu and next_cpu CPUStateAndreas Färber2013-07-091-13/+12
* cpu: Turn cpu_unassigned_access() into a CPUState hookAndreas Färber2013-06-281-4/+9
* cpu: Pass CPUState to cpu_interrupt()Andreas Färber2013-03-121-4/+4
* exec: Pass CPUState to cpu_reset_interrupt()Andreas Färber2013-03-121-3/+2
* cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber2013-03-121-3/+7
* target-mips: Use mul[us]2 in [D]MULT[U] insnsRichard Henderson2013-02-231-12/+0
* target-mips: Unfuse {,N}M{ADD,SUB}.fmtRichard Sandiford2013-01-311-8/+17
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