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path: root/target-mips/cpu.h
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* target-*: Drop cpu_gen_code defineRichard Henderson2015-10-071-1/+0
* target-mips: Add delayed branch state to insn_startRichard Henderson2015-10-071-0/+1
* mips: Remove ELF_MACHINE from cpu.hPeter Crosthwaite2015-09-251-2/+0
* target-mips: improve exception handlingPavel Dovgaluk2015-09-181-0/+24
* tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt2015-09-111-1/+1
* target-mips: update mips32r5-generic into P5600Yongbok Kim2015-08-131-1/+1
* cpu-exec: Purge all uses of ENV_GET_CPU()Peter Crosthwaite2015-07-091-1/+1
* target-mips: add MTHC0 and MFHC0 instructionsLeon Alrae2015-06-121-0/+1
* target-mips: add CP0.PageGrain.ELPA supportLeon Alrae2015-06-121-2/+25
* target-mips: extend selected CP0 registers to 64-bits in MIPS32Leon Alrae2015-06-121-7/+7
* target-mips: add ERETNC instruction and Config5.LLB bitLeon Alrae2015-06-111-0/+1
* target-mips: add Config5.FRE support allowing Status.FR=0 emulationLeon Alrae2015-06-111-2/+11
* Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150311' into stagingPeter Maydell2015-03-111-2/+17
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| * target-mips: add missing MSACSR and restore fp_status and hflagsLeon Alrae2015-03-111-0/+17
| * target-mips: replace cpu_save/cpu_load with VMStateDescriptionLeon Alrae2015-03-111-2/+0
* | cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost2015-03-101-8/+1
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* exec.c: Drop TARGET_HAS_ICE define and checksPeter Maydell2015-01-201-1/+0
* target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki2014-12-161-0/+12
* target-mips: Correct 32-bit address space wrappingMaciej W. Rozycki2014-12-161-3/+5
* target-mips: Tighten ISA level checksMaciej W. Rozycki2014-12-161-3/+4
* target-mips: Correct the writes to Status and Cause registers via gdbstubMaciej W. Rozycki2014-12-161-0/+89
* target-mips: Make CP0.Config4 and CP0.Config5 registers signedMaciej W. Rozycki2014-12-161-4/+4
* mips: Add macros for CP0.Config3 and CP0.Config4 bitsMaciej W. Rozycki2014-11-071-0/+13
* target-mips: remove duplicated mips/ieee mapping functionYongbok Kim2014-11-031-0/+4
* target-mips: add MSA defines and data structureYongbok Kim2014-11-031-2/+50
* target-mips: CP0_Status.CU0 no longer allows the user to access CP0Leon Alrae2014-11-031-1/+2
* target-mips: implement forbidden slotLeon Alrae2014-11-031-1/+2
* target-mips: add Config5.SBRILeon Alrae2014-11-031-2/+9
* target-mips: update cpu_save/cpu_load to support new registersLeon Alrae2014-11-031-1/+1
* target-mips: add BadInstr and BadInstrP supportLeon Alrae2014-11-031-0/+6
* target-mips: add TLBINV supportLeon Alrae2014-11-031-0/+7
* target-mips: add new Read-Inhibit and Execute-Inhibit exceptionsLeon Alrae2014-11-031-1/+4
* target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae2014-11-031-0/+4
* target-mips: add RI and XI fields to TLB entryLeon Alrae2014-11-031-0/+11
* target-mips: add KScratch registersLeon Alrae2014-11-031-0/+3
* target-mips: fix broken MIPS16 and microMIPSYongbok Kim2014-10-141-6/+7
* target-mips: Status.UX/SX/KX enable 32-bit address wrappingLeon Alrae2014-10-131-4/+14
* target-mips: implement UserLocal RegisterPetar Jovanovic2014-06-181-4/+7
* softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini2014-06-051-0/+1
* target-mips: Avoid shifting left into sign bitPeter Maydell2014-03-271-1/+1
* cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-0/+1
* cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber2014-03-131-3/+2
* cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2014-03-131-28/+0
* target-mips: add support for CP0_Config5Petar Jovanovic2014-02-101-0/+10
* target-mips: add support for CP0_Config4Petar Jovanovic2014-02-101-0/+3
* misc: Replace 'struct QEMUTimer' by 'QEMUTimer'Stefan Weil2013-12-021-1/+1
* cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber2013-07-231-7/+0
* linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-userPeter Maydell2013-07-091-13/+0
* cpu: Turn cpu_unassigned_access() into a CPUState hookAndreas Färber2013-06-281-2/+3
* linux-user: Save the correct resume address for MIPS signal handlingKwok Cheung Yeung2013-05-201-0/+1
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