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* event-notifier: Add "is_external" parameterFam Zheng2019-11-291-3/+3
| | | | | | | | | | All callers pass "false" keeping the old semantics. The windows implementation doesn't distinguish the flag yet. On posix, it is passed down to the underlying aio context. Signed-off-by: Fam Zheng <famz@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* target-i386: Set AMD alias bits after filtering CPUID dataEduardo Habkost2019-11-291-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | QEMU complains about -cpu host on an AMD machine: warning: host doesn't support requested feature: CPUID.80000001H:EDX [bit 0] For bits 0,1,3,4,5,6,7,8,9,12,13,14,15,16,17,23,24. KVM_GET_SUPPORTED_CPUID and and x86_cpu_get_migratable_flags() don't handle the AMD CPUID aliases bits, making x86_cpu_filter_features() print warnings and clear those CPUID bits incorrectly. To avoid hacking x86_cpu_get_migratable_flags() to handle CPUID_EXT2_AMD_ALIASES (just like the existing hack inside kvm_arch_get_supported_cpuid()), simply move the CPUID_EXT2_AMD_ALIASES code in x86_cpu_realizefn() after the x86_cpu_filter_features() call. This will probably make the CPUID_EXT2_AMD_ALIASES hack in kvm_arch_get_supported_cpuid() unnecessary, too. The hack will be removed in a follow-up patch after v2.6.0. Reported-by: Radim Krčmář <rkrcmar@redhat.com> Tested-by: Radim Krčmář <rkrcmar@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* target-i386: check for PKU even for non-writable pagesPaolo Bonzini2019-11-291-8/+10
| | | | | | | | | | | | | | | | | | | | | Xiao Guangrong ran kvm-unit-tests on an actual machine with PKU and found that it fails: test pte.p pte.user pde.p pde.user pde.a pde.pse pkru.wd pkey=1 user write efer.nx cr4.pke: FAIL: error code 27 expected 7 Dump mapping: address: 0x123400000000 ------L4: 2ebe007 ------L3: 2ebf007 ------L2: 8000000020000a5 (All failures are combinations of "pde.user pde.p pkru.wd pkey=1", plus either "pde.pse" or "pte.p pte.user", plus one of "user cr0.wp", "cr0.wp" or "user", plus unimportant bits such as accessed/dirty or efer.nx). So PFEC.PKEY is set even if the ordinary check failed (which it did because pde.w is zero). Adjust QEMU to match behavior of silicon. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: assert that KVM_GET/SET_MSRS can set all requested MSRsPaolo Bonzini2019-11-291-4/+30
| | | | | | This would have caught the bug in the previous patch. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: do not pass MSR_TSC_AUX to KVM ioctls if CPUID bit is not setPaolo Bonzini2019-11-291-0/+3
| | | | | | | | | | | | | | KVM does not let you read or write this MSR if the corresponding CPUID bit is not set. This in turn causes MSRs that come after MSR_TSC_AUX to be ignored by KVM_SET_MSRS. One visible symptom is that s3.flat from kvm-unit-tests fails with CPUs that do not have RDTSCP, because the SMBASE is not reset to 0x30000 after reset. Fixes: c9b8f6b6210847b4381c5b2ee172b1c7eb9985d6 Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386/kvm: Hyper-V VMBus hypercalls blank handlersAndrey Smetanin2019-11-291-0/+12
| | | | | | | | | | | | | | | | | | | | | Add Hyper-V VMBus hypercalls blank handlers which just returns error code - HV_STATUS_INVALID_HYPERCALL_CODE. This is required when the synthetic interrupt controller is active. Fixes: 50efe82c3c27195162dd8df273eadd77d8aecad3 Signed-off-by: Andrey Smetanin <asmetanin@virtuozzo.com> Reviewed-by: Roman Kagan <rkagan@virtuozzo.com> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Richard Henderson <rth@twiddle.net> CC: Eduardo Habkost <ehabkost@redhat.com> CC: "Andreas Färber" <afaerber@suse.de> CC: Marcelo Tosatti <mtosatti@redhat.com> CC: Roman Kagan <rkagan@virtuozzo.com> CC: Denis V. Lunev <den@openvz.org> CC: kvm@vger.kernel.org Message-Id: <1456309368-29769-2-git-send-email-asmetanin@virtuozzo.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: implement PKE for TCGPaolo Bonzini2019-11-297-5/+110
| | | | | | Tested with kvm-unit-tests. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* util: move declarations out of qemu-common.hVeronia Bahaa2019-11-291-0/+1
| | | | | | | | | | Move declarations out of qemu-common.h for functions declared in utils/ files: e.g. include/qemu/path.h for utils/path.c. Move inline functions out of qemu-common.h and into new files (e.g. include/qemu/bcd.h) Signed-off-by: Veronia Bahaa <veroniabahaa@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* include/qemu/osdep.h: Don't include qapi/error.hMarkus Armbruster2019-11-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the Error typedef. Since then, we've moved to include qemu/osdep.h everywhere. Its file comment explains: "To avoid getting into possible circular include dependencies, this file should not include any other QEMU headers, with the exceptions of config-host.h, compiler.h, os-posix.h and os-win32.h, all of which are doing a similar job to this file and are under similar constraints." qapi/error.h doesn't do a similar job, and it doesn't adhere to similar constraints: it includes qapi-types.h. That's in excess of 100KiB of crap most .c files don't actually need. Add the typedef to qemu/typedefs.h, and include that instead of qapi/error.h. Include qapi/error.h in .c files that need it and don't get it now. Include qapi-types.h in qom/object.h for uint16List. Update scripts/clean-includes accordingly. Update it further to match reality: replace config.h by config-target.h, add sysemu/os-posix.h, sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h comment quoted above similarly. This reduces the number of objects depending on qapi/error.h from "all of them" to less than a third. Unfortunately, the number depending on qapi-types.h shrinks only a little. More work is needed for that one. Signed-off-by: Markus Armbruster <armbru@redhat.com> [Fix compilation without the spice devel packages. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* kvm: Remove x2apic feature from CPU model when kernel_irqchip is offLan Tianyu2019-11-291-0/+4
| | | | | | | | | | | | | | x2apic feature is in the kvm_default_props and automatically added to all CPU models when KVM is enabled. But userspace devices don't support x2apic which can't be enabled without the in-kernel irqchip. It will trigger warning of "host doesn't support requested feature: CPUID.01H:ECX.x2apic [bit 21]" when kernel_irqchip is off. This patch is to fix it via removing x2apic feature when kernel_irqchip is off. Signed-off-by: Lan Tianyu <tianyu.lan@intel.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* hyperv: cpu hotplug fix with HyperV enabledDenis V. Lunev2019-11-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | With Hyper-V enabled CPU hotplug stops working. The CPU appears in device manager on Windows but does not appear in peformance monitor and control panel. The root of the problem is the following. Windows checks HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE bit in CPUID. The presence of this bit is enough to cure the situation. The bit should be set when CPU hotplug is allowed for HyperV VM. The check that hot_add_cpu callback is defined is enough from the protocol point of view. Though this callback is defined almost always thus there is no need to export that knowledge in the other way. Signed-off-by: Denis V. Lunev <den@openvz.org> Reviewed-by: Roman Kagan <rkagan@virtuozzo.com> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Richard Henderson <rth@twiddle.net> CC: Eduardo Habkost <ehabkost@redhat.com> CC: "Andreas Färber" <afaerber@suse.de> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* target-i386: Dump unknown opcodes with -d unimpRichard Henderson2019-11-291-44/+83
| | | | | | | | We discriminate here between opcodes that are illegal in the current cpu mode or with illegal arguments (such as modrm.mod == 3) and encodings that are unknown (such as an unimplemented isa extension). Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Fix inhibit irq mask handlingRichard Henderson2019-11-291-39/+37
| | | | | | | | | | | The patch in 7f0b714 was too simplistic, in that we wound up setting the flag and then resetting it immediately in gen_eob. Fixes the reported boot problem with Windows XP. Reported-by: Hervé Poussineau <hpoussin@reactos.org> Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Use gen_nop_modrm for prefetch instructionsRichard Henderson2019-11-291-3/+2
| | | | | Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Fix addr16 prefixPaolo Bonzini2019-11-291-7/+7
| | | | | | | | | | | | | | | | | | | | While ADDSEG will only be false in 16-bit mode for LEA, it can be false even in other cases when 16-bit addresses are obtained via the 67h prefix in 32-bit mode. In this case, gen_lea_v_seg forgets to add a nonzero FS or GS base if CS/DS/ES/SS are all zero. This case is pretty rare but happens when booting Windows 95/98, and this patch fixes it. The bug is visible since commit d6a291498, but it was introduced together with gen_lea_v_seg and it probably could be reproduced with a "addr16 gs movsb" instruction as early as in commit ca2f29f555805d07fb0b9ebfbbfc4e3656530977. Reported-by: Hervé Poussineau <hpoussin@reactos.org> Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1456931078-21635-1-git-send-email-pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Fix SMSW for 64-bit modeRichard Henderson2019-11-291-6/+8
| | | | | | | | | In non-64-bit modes, the instruction always stores 16 bits. But in 64-bit mode, when the destination is a register, the instruction can write 32 or 64 bits. Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Fix SMSW and LMSW from/to registerPaolo Bonzini2019-11-291-16/+22
| | | | | | | | | | | | SMSW and LMSW accept register operands, but commit 1906b2a ("target-i386: Rearrange processing of 0F 01", 2016-02-13) did not account for that. Fixes: 1906b2af7c2345037d9b2fdf484b457b5acd09d1 Reported-by: Hervé Poussineau <hpoussin@reactos.org> Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1456845134-18812-1-git-send-email-pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Avoid repeated calls to the bnd_jmp helperPaolo Bonzini2019-11-291-5/+5
| | | | | | | | | | Two flags were tested the wrong way. Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1456845145-18891-1-git-send-email-pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net> [rth: Fixed enable test as well.]
* tcg: Add type for vCPU pointersLluís Vilanova2019-11-291-1/+1
| | | | | | | | | | | | | | | | | | | | Adds the 'TCGv_env' type for pointers to 'CPUArchState' objects. The tracing infrastructure later needs to differentiate between regular pointers and pointers to vCPUs. Also changes all targets to use the new 'TCGv_env' type instead of the generic 'TCGv_ptr'. As of now, the change is merely cosmetic ('TCGv_env' translates into 'TCGv_ptr'), but that could change in the future to enforce the difference. Note that a 'TCGv_env' type (for 'CPUState') is not added, since all helpers currently receive the architecture-specific pointer ('CPUArchState'). Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Acked-by: Richard Henderson <rth@twiddle.net> Message-id: 145641859552.30295.7821536833590725201.stgit@localhost Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* target-i386: fix confusion in xcr0 bit position vs. maskPaolo Bonzini2019-11-294-42/+59
| | | | | | | | | | The xsave and xrstor helpers are accessing the x86_ext_save_areas array using a bit mask instead of a bit position. Provide two sets of XSTATE_* definitions and use XSTATE_*_BIT when a bit position is requested. Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* all: Clean up includesPeter Maydell2019-11-293-2/+1
| | | | | | | | | | Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com>
* cpu: Clean up includesPeter Maydell2019-11-291-4/+1
| | | | | | | | | Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-i386: Implement FSGSBASERichard Henderson2019-11-294-2/+50
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Enable CR4/XCR0 features for user-modeRichard Henderson2019-11-291-2/+22
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Clear bndregs during legacy near jumpsRichard Henderson2019-11-293-0/+29
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Implement BNDLDX, BNDSTXRichard Henderson2019-11-293-0/+158
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Update BNDSTATUS for exceptions raised by BOUNDRichard Henderson2019-11-291-0/+6
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Implement BNDCL, BNDCU, BNDCNRichard Henderson2019-11-293-1/+53
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Implement BNDMOVRichard Henderson2019-11-291-1/+72
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Implement BNDMKRichard Henderson2019-11-291-1/+57
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Split up gen_lea_modrmRichard Henderson2019-11-291-114/+85
| | | | | | | This is immediately usable by lea and multi-byte nop, and will be required to implement parts of the mpx spec. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Perform set/reset_inhibit_irq inlineRichard Henderson2019-11-293-21/+28
| | | | | | With helpers that can be reused for other things. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Enable control registers for MPXRichard Henderson2019-11-2910-26/+189
| | | | | | Enable and disable at CPL changes, MSR changes, and XRSTOR changes. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Implement XSAVEOPTRichard Henderson2019-11-294-11/+43
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Add XSAVE extensionRichard Henderson2019-11-296-24/+241
| | | | | | | This includes XSAVE, XRSTOR, XGETBV, XSETBV, which are all related, as well as the associate cpuid bits. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Rearrange processing of 0F AERichard Henderson2019-11-291-52/+72
| | | | | | | | Rather than nesting tests of OP, MOD, and RM, decode them all at once with a switch. Also, add some missing #UD checks for e.g. incorrect LOCK prefix. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Rearrange processing of 0F 01Richard Henderson2019-11-291-223/+247
| | | | | | | | Rather than nesting tests of OP, MOD, and RM, decode them all at once with a switch. Fixes incorrect decoding of AMD Pacifica extensions (aka vmrun et al) via op==2 path. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Split fxsave/fxrstor implementationRichard Henderson2019-11-293-82/+101
| | | | | | We will be able to reuse these pieces for XSAVE/XRSTOR. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: fix PSE36 modePaolo Bonzini2019-11-291-2/+2
| | | | | | | | | | (pde & 0x1fe000) is a 32-bit integer; when shifting it into bits 39-32 the result is zero. Fix it by making the mask (and thus the result of the AND) a 64-bit integer. Reported by Coverity. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Deconstruct the cpu_T arrayRichard Henderson2019-11-291-614/+624
| | | | | | | | | | All references to cpu_T are done with a constant index. It aids readability to decompose the array into two scalar variables. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1436426122-12276-11-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Tidy gen_add_A0_imRichard Henderson2019-11-291-22/+5
| | | | | | | | | | | | Merge gen_op_addl_A0_im and gen_op_addq_A0_im into gen_add_A0_im and clean up the ifdef. Replace the one remaining user of gen_op_addl_A0_im with gen_add_A0_im. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-10-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Rewrite leaveRichard Henderson2019-11-291-14/+15
| | | | | | | | | Unify the code across stack pointer widths. Fix the note about not updating ESP before the potential exception. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-9-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Rewrite gen_enter inlineRichard Henderson2019-11-293-137/+34
| | | | | | | | | | Use gen_lea_v_seg for centralized segment base knowledge. Unify code across 32- and 64-bit. Fix note about "must save state" before using the out-of-line helpers. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-8-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Use gen_lea_v_seg in pusha/popaRichard Henderson2019-11-291-27/+23
| | | | | | | | | More centralization of handling of segment bases. Also fixes the note about 16-bit wrap around not fully handled. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-7-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Access segs via TCG registersRichard Henderson2019-11-291-24/+28
| | | | | | | | | | | | Having segs[].base as a register significantly improves code generation for real and protected modes, particularly for TBs that have multiple memory references where the segment base can be held in a hard register through the TB. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-6-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Use gen_lea_v_seg in stack subroutinesRichard Henderson2019-11-291-39/+13
| | | | | | | | | I.e. gen_push_v, gen_pop_T0, gen_stack_A0. More centralization of handling of segment bases. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-5-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Use gen_lea_v_seg in gen_lea_modrmRichard Henderson2019-11-291-59/+23
| | | | | | | | Centralize handling of segment bases. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-4-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Introduce mo_stacksizeRichard Henderson2019-11-291-14/+10
| | | | | | | | Centralize computation of a MO_SIZE for the stack pointer. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-3-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Create gen_lea_v_segRichard Henderson2019-11-291-107/+53
| | | | | | | | | | Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case; use this new function to implement gen_string_movl_A0_EDI, gen_string_movl_A0_ESI, gen_add_A0_ds_seg. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-2-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson2019-11-291-5/+5
| | | | | | | | Thus, use cpu_env as the parameter, not TCG_AREG0 directly. Update all uses in the translators. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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