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* Fix off-by-one unwinding error.pbrook2008-05-251-5/+0
* Fix A20 debug dumps.pbrook2008-05-241-2/+2
* Fix ARM conditional branch bug.pbrook2008-05-241-28/+25
* use debug_insn_start to have nicer debug tracesbellard2008-05-221-5/+2
* proper helper definition registering (all targets must do that)bellard2008-05-223-353/+361
* optimization of shifts by a constantbellard2008-05-221-4/+68
* lahf/sahf cpuid testbellard2008-05-222-9/+6
* cmpxchg8b fix - added cmpxchg16bbellard2008-05-223-7/+47
* cmpxchg 64 bit fixbellard2008-05-221-4/+10
* fxsave/fxrstor 64 bit fixbellard2008-05-221-2/+20
* converted conditional jumps, SET and CMOVx to TCGbellard2008-05-214-840/+421
* converted env access to TCGbellard2008-05-212-67/+32
* convert eflags manipulation insns to TCGbellard2008-05-215-148/+46
* convert remaining segment handling to TCGbellard2008-05-213-49/+38
* converted LSL/LAR/VERW/VERR to TCG - force 16 bit memory access for LSL/LARbellard2008-05-214-61/+39
* suppressed no longer used opsbellard2008-05-212-17/+0
* converted INTO/CMPXCHG8B to TCGbellard2008-05-214-20/+12
* converted BCD ops to TCGbellard2008-05-212-38/+6
* converted MUL/IMUL to TCGbellard2008-05-213-133/+129
* converted string OPs and LOOP insns to TCGbellard2008-05-183-294/+147
* fixed INC/DEC condition codesbellard2008-05-181-1/+1
* converted sign extension ops to TCGbellard2008-05-172-76/+31
* MONITOR insn address generation fix - converted XLAT to TCGbellard2008-05-172-40/+20
* BSR/BSF TCG conversionbellard2008-05-174-72/+54
* converted bit test operations to TCGbellard2008-05-172-98/+53
* moved eflags computation outside op.cbellard2008-05-174-293/+296
* converted adc, sbb, cmpxchg to TCGbellard2008-05-173-305/+151
* converted condition code supprot to TCG - converted shift ops to TCGbellard2008-05-179-1132/+762
* converted more helpers to TCG - fixed some SVM issuesbellard2008-05-1510-485/+404
* i386 specific TODObellard2008-05-131-0/+29
* compilation fixbellard2008-05-121-1/+3
* converted more helpers to TCGbellard2008-05-125-647/+498
* removed unused codebellard2008-05-121-6/+0
* FPU fixesbellard2008-05-121-11/+11
* converted x87 FPU ops to TCGbellard2008-05-125-945/+756
* converted SSE/MMX ops to TCGbellard2008-05-126-671/+715
* use TCG for MMX/SSE memory accessesbellard2008-05-123-221/+58
* char is only for stringsbellard2008-05-121-3/+3
* no need to define global registers in cpu-exec.cbellard2008-05-101-41/+4
* Correctly save and restore env->a20_mask now that it is a 64-bitaurel322008-05-041-2/+6
* remove target ifdefs from vl.caurel322008-05-041-0/+264
* Factorize code in translate.caurel322008-04-281-0/+23
* Use correct types to enable > 2G support, based on a patch fromaurel322008-04-272-3/+26
* Fix PHYS_ADDR_MASK: upper bits of a PTE are reserved so they are 52 bitsaurel322008-04-221-1/+2
* x86/x86-64 MMU PAE fixesaurel322008-04-222-20/+24
* x86: Introduce CPU_INTERRUPT_NMIaurel322008-04-133-2/+7
* Remove osdep.c/qemu-img code duplicationaurel322008-04-111-0/+1
* Remove unused phys_ram_base definition from target-i386/helper.c.aurel322008-04-111-1/+0
* Check for 3DNow! CPUID at translation timeaurel322008-04-091-2/+13
* Fix typo in x86 CPU definitions introduced in r4181aurel322008-04-081-1/+1
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