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* converted string OPs and LOOP insns to TCGbellard2008-05-183-294/+147
* fixed INC/DEC condition codesbellard2008-05-181-1/+1
* converted sign extension ops to TCGbellard2008-05-172-76/+31
* MONITOR insn address generation fix - converted XLAT to TCGbellard2008-05-172-40/+20
* BSR/BSF TCG conversionbellard2008-05-174-72/+54
* converted bit test operations to TCGbellard2008-05-172-98/+53
* moved eflags computation outside op.cbellard2008-05-174-293/+296
* converted adc, sbb, cmpxchg to TCGbellard2008-05-173-305/+151
* converted condition code supprot to TCG - converted shift ops to TCGbellard2008-05-179-1132/+762
* converted more helpers to TCG - fixed some SVM issuesbellard2008-05-1510-485/+404
* i386 specific TODObellard2008-05-131-0/+29
* compilation fixbellard2008-05-121-1/+3
* converted more helpers to TCGbellard2008-05-125-647/+498
* removed unused codebellard2008-05-121-6/+0
* FPU fixesbellard2008-05-121-11/+11
* converted x87 FPU ops to TCGbellard2008-05-125-945/+756
* converted SSE/MMX ops to TCGbellard2008-05-126-671/+715
* use TCG for MMX/SSE memory accessesbellard2008-05-123-221/+58
* char is only for stringsbellard2008-05-121-3/+3
* no need to define global registers in cpu-exec.cbellard2008-05-101-41/+4
* Correctly save and restore env->a20_mask now that it is a 64-bitaurel322008-05-041-2/+6
* remove target ifdefs from vl.caurel322008-05-041-0/+264
* Factorize code in translate.caurel322008-04-281-0/+23
* Use correct types to enable > 2G support, based on a patch fromaurel322008-04-272-3/+26
* Fix PHYS_ADDR_MASK: upper bits of a PTE are reserved so they are 52 bitsaurel322008-04-221-1/+2
* x86/x86-64 MMU PAE fixesaurel322008-04-222-20/+24
* x86: Introduce CPU_INTERRUPT_NMIaurel322008-04-133-2/+7
* Remove osdep.c/qemu-img code duplicationaurel322008-04-111-0/+1
* Remove unused phys_ram_base definition from target-i386/helper.c.aurel322008-04-111-1/+0
* Check for 3DNow! CPUID at translation timeaurel322008-04-091-2/+13
* Fix typo in x86 CPU definitions introduced in r4181aurel322008-04-081-1/+1
* Remove hardcoded values in x86 CPU definitionsaurel322008-04-081-4/+11
* 3DNow! instruction set emulationaurel322008-04-084-10/+246
* x86-64: recompute DF after eflags has been modified when emulating SYSCALLaurel322008-03-281-0/+1
* Fix some functions declared () rather than (void) (Ian Jackson)blueswir12008-03-092-2/+2
* More helper types, rearrange generic definitionsblueswir12008-02-241-64/+0
* Add TCG variable opaque type.pbrook2008-02-031-3/+3
* NMI and INTR events injection should not be handled as software interrupts (B...balrog2008-02-031-2/+2
* Make SVM env->cr[8] a valid register (patch from TeLeMan).balrog2008-02-032-2/+6
* use the TCG code generatorbellard2008-02-016-1160/+794
* Correct the max cpuid level for each x86 cpu model (Dan Kenigsberg).balrog2007-12-241-1/+8
* SVM enabled processor should provide cpuid Fn8000_000A (Bernhard Kauer).balrog2007-12-242-1/+7
* Fix cmpxchg8b translation (Bernhard Kauer).balrog2007-12-241-1/+1
* Make SVM IOIO intercept check all needed bits, by Bernhard Kauer.balrog2007-12-091-1/+2
* Add rdpmc SVM intercept, by Bernhard Kauer.balrog2007-12-094-0/+22
* Fix spelling typo, by Dan Kenigsberg.ths2007-12-091-1/+1
* Handle cpu_model in copy_cpu(), by Kirill A. Shutemov.ths2007-12-091-0/+1
* typo fixbellard2007-11-211-1/+1
* Add statics and missing #includes for prototypes.pbrook2007-11-181-2/+2
* x86_64 linux user emulationbellard2007-11-142-3/+20
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