summaryrefslogtreecommitdiffstats
path: root/target-i386
Commit message (Collapse)AuthorAgeFilesLines
...
* v2: properly save kvm system time msr registersGlauber Costa2009-12-123-0/+20
| | | | | | | | | | | | | | | | | Currently, the msrs involved in setting up pvclock are not saved over migration and/or save/restore. This patch puts their value in special fields in our CPUState, and deal with them using vmstate. kvm also has to account for it, by including them in the msr list for the ioctls. This is a backport from qemu-kvm.git [v2: sucessfully build without kerneldir ] Signed-off-by: Glauber Costa <glommer@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* kvm: x86: Save/restore exception_indexJan Kiszka2009-12-121-0/+1
| | | | | | | | | | | As KVM now makes use of exception_index to keep pending exceptions, we have to save&restore this field as well. NOTE: We have to nail the arch-independent exception_index down to a certain bit width for proper vmstate processing, namely to 32 bit. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* cpuid: Fix multicore setup on IntelAndre Przywara2009-12-071-15/+31
| | | | | | | | | | | | | | The multicore CPUID code detects whether the guest is an Intel or an AMD CPU, because the Linux kernel is picky about the CmpLegacy bit. KVM by default passes through the host's vendor, which was not catched by the code. So fork out the vendor determining bits into a separate function to be used from both places and always get the real vendor. This fixes KVM's multicore setup on Intel CPUs. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Reported-by: Dietmar Maurer <dietmar@proxmox.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* kvm: x86: Fix initial kvm_has_msr_starJan Kiszka2009-12-071-2/+2
| | | | | | | | | | | | | KVM_GET_MSR_INDEX_LIST returns -E2BIG when the provided space is too small for all MSRs. But this is precisely the error we trigger with the initial request in order to obtain that size. Do not fail in that case. This caused a subtle corruption of the guest state as MSR_STAR was not properly saved/restored. The corruption became visible with latest kvm optimizing the MSR updates. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* kvm: x86: Add support for VCPU event statesJan Kiszka2009-12-033-0/+88
| | | | | | | | | This patch extends the qemu-kvm state sync logic with support for KVM_GET/SET_VCPU_EVENTS, giving access to yet missing exception, interrupt and NMI states. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* kvm: x86: Fix merge artifact of f8d926e9 about mp_stateJan Kiszka2009-12-031-4/+4
| | | | | Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* kvm: x86: Refactor use of interrupt_bitmapJan Kiszka2009-11-173-31/+21
| | | | | | | | | | Drop interrupt_bitmap from the cpustate and solely rely on the integer interupt_injected. This prepares us for the new injected-interrupt interface, which will deprecate the bitmap, while preserving compatibility. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* kvm: Add arch reset handlerJan Kiszka2009-11-171-0/+4
| | | | | | | Will be required by succeeding changes. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* kvm: Move KVM mp_state accessors to i386-specific codeHollis Blanchard2009-11-121-0/+20
| | | | | | | Unbreaks PowerPC and S390 KVM builds. Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* user: move CPU reset call to main.c for x86/PPC/SparcBlue Swirl2009-11-071-3/+0
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* v3: don't call reset functions on cpu initializationGlauber Costa2009-11-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | There is absolutely no need to call reset functions when initializing devices. Since we are already registering them, calling qemu_system_reset() should suffice. Actually, it is what happens when we reboot the machine, and using the same process instead of a special case semantics will even allow us to find bugs easier. Furthermore, the fact that we initialize things like the cpu quite early, leads to the need to introduce synchronization stuff like qemu_system_cond. This patch removes it entirely. All we need to do is call qemu_system_reset() only when we're already sure the system is up and running I tested it with qemu (with and without io-thread) and qemu-kvm, and it seems to be doing okay - although qemu-kvm uses a slightly different patch. [ v2: user mode still needs cpu_reset, so put it in ifdef. ] [ v3: leave qemu_system_cond for now. ] Signed-off-by: Glauber Costa <glommer@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* vmstate: Add version arg to VMSTATE_SINGLE_TEST()Juan Quintela2009-10-271-1/+1
| | | | | | This allows to define VMSTATE_SINGLE with VMSTATE_SINGLE_TEST Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* target-i386: implement lzcnt emulationAndre Przywara2009-10-233-14/+38
| | | | | | | | | | | | | lzcnt is a AMD Phenom/Barcelona added instruction returning the number of leading zero bits in a word. As this is similar to the "bsr" instruction, reuse the existing code. There need to be some more changes, though, as lzcnt always returns a valid value (in opposite to bsr, which has a special case when the operand is 0). lzcnt is guarded by the ABM CPUID bit (Fn8000_0001:ECX_5). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* x86: add 'static' to please SparseBlue Swirl2009-10-181-5/+5
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-i386: fix ARPLLaurent Desnogues2009-10-061-3/+7
| | | | | | | | The arpl implementation in target-i386/translate.c uses cpu_A0 temporary across a brcond op. This patch fixes that issue. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-i386: move recently added vmstate fields at the end of the structureAurelien Jarno2009-10-051-4/+6
| | | | | | | This reduce the impact on hosts that have addressing modes with limited offsets. Suggested by Laurent Desnogues. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* x86: fix miss mergeJuan Quintela2009-10-051-1/+2
| | | | | | | | There was a missmerge, and then we got a tail recursive call to cpu_post_load without case base :) Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* gdbstub: x86: Switch 64/32 bit registers dynamicallyJan Kiszka2009-10-051-2/+5
| | | | | | | | | | | | | | | | | Commit 56aebc891674cd2d07b3f64183415697be200084 changed gdbstub in way that debugging 32 or 16-bit guest code is no longer possible with qemu for x86_64 guest CPUs. Since that commit, qemu only provides registers sets for 64-bit, forcing current and foreseeable gdb to also switch its architecture to 64-bit. And this breaks if the inferior is 32 or 16 bit. No question, this is a gdb issue. But, as it was confirmed in several discusssions with gdb people, it is a non-trivial thing to fix. So until qemu finds a gdb version attach with a rework x86 support, we have to work around it by switching the register layout as the guest switches its execution mode between 16/32 and 64 bit. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: port cpu to vmstateJuan Quintela2009-10-051-259/+240
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: factor out cpu_get/put_fpreg()Juan Quintela2009-10-051-72/+137
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: factor out cpu_get/put_mttr_var()Juan Quintela2009-10-051-4/+24
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: factor out cpu_get/put_xmm_reg()Juan Quintela2009-10-051-4/+24
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: factor out cpu_pre/post_load()Juan Quintela2009-10-051-18/+39
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: factor out cpu_pre_save()Juan Quintela2009-10-051-21/+32
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: port segments to vmstateJuan Quintela2009-10-051-8/+16
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: split MTRRVar unionJuan Quintela2009-10-051-4/+6
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: split FPReg unionJuan Quintela2009-10-051-8/+10
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: mcg_cap is never 0Juan Quintela2009-10-051-12/+8
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: send mce_banks as an arrayJuan Quintela2009-10-051-10/+4
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: mce_banks always have the same sizeJuan Quintela2009-10-053-5/+4
| | | | | | | | mce_banks is always MCE_BANKS_DEF * 4 in size, value never change CC: Huang Ying <ying.huang@intel.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: add fpregs_format_vmstateJuan Quintela2009-10-052-7/+6
| | | | | | | Don't even ask, being able to load/save between 64<->80bit floats should be forbidden Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: add pending_irq_vmstate to the stateJuan Quintela2009-10-052-9/+8
| | | | | | | It is needed to save the interrupt_bitmap Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: add fptag_vmstate to the stateJuan Quintela2009-10-052-9/+10
| | | | | | | It is needed to store fptags Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: fpus is uint16_t not unsigned intJuan Quintela2009-10-052-9/+10
| | | | | | | We save more that fpus on that 16 bits (fpstt), we need an additional field Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: fpuc is uint16_t not unsigned intJuan Quintela2009-10-052-7/+5
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: make a20_mask int32_tJuan Quintela2009-10-053-11/+6
| | | | | | | | | | This makes the savevm code correct, and sign extensins gives us exactly what we need (namely, sign extend to 64 bits when used with 64bit addresess. Once there, change 0x100000 for 1 << 20, that maks all a20 use the same syntax. Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: hflags is not modified at all, just save it directlyJuan Quintela2009-10-051-8/+3
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* target-i386: Fix exceptions for fxsave/fxrstorKevin Wolf2009-10-042-4/+14
| | | | | | | | | | | | This patch corrects the following aspects of exception generation in fxsave/fxrstor: * Generate #GP if the operand is not aligned to a 16 byte boundary * Generate #UD if the LOCK prefix is used * For CR0.EM = 1 #NM is generated, not #UD Signed-off-by: Kevin Wolf <mail@kevin-wolf.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-i386: add RDTSCP supportAndre Przywara2009-10-045-16/+63
| | | | | | | | | | | | | | RDTSCP reads the time stamp counter and atomically also the content of a 32-bit MSR, which can be freely set by the OS. This allows CPU local data to be queried by userspace. Linux uses this to allow a fast implementation of the getcpu() syscall, which uses the vsyscall page to avoid a context switch. AMD CPUs since K8RevF and Intel CPUs since Nehalem support this instruction. RDTSCP is guarded by the RDTSCP CPUID bit (Fn8000_0001:EDX[27]). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-i386: add SSE4a instruction supportAndre Przywara2009-10-043-2/+85
| | | | | | | | | | | | | | This adds support for the AMD Phenom/Barcelona's SSE4a instructions. Those include insertq and extrq, which are doing shift and mask on XMM registers, in two versions (immediate shift/length values and stored in another XMM register). Additionally it implements movntss, movntsd, which are scalar non-temporal stores (avoiding cache trashing). These are implemented as normal stores, though. SSE4a is guarded by the SSE4A CPUID bit (Fn8000_0001:ECX[6]). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-i386: add lock mov cr0 = cr8Andre Przywara2009-10-041-0/+4
| | | | | | | | | | AMD CPUs featuring a shortcut to access CR8 even from 32-bit mode. If you use the LOCK prefix with "mov CR0", it accesses CR8 instead. This behavior is guarded by the CR8_LEGACY CPUID bit (Fn8000_0001:ECX[1]). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Revert "Get rid of _t suffix"Anthony Liguori2009-10-012-15/+15
| | | | | | | | | | | | In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Get rid of _t suffixmalc2009-10-012-15/+15
| | | | | | | Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
* x86: use globals for CPU registersLaurent Desnogues2009-09-301-71/+125
| | | | | | Use globals for the 8 or 16 CPU registers on i386 and x86_64. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-i386: kill a tmp registerAurelien Jarno2009-09-271-4/+3
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-i386: use subfi instead of sub with a non-freed constantAurelien Jarno2009-09-271-7/+7
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* gcc wants 1st static and then constJuan Quintela2009-09-251-1/+1
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* ioports: remove unused env parameter and compile only onceBlue Swirl2009-09-201-6/+6
| | | | | | | The CPU state parameter is not used, remove it and adjust callers. Now we can compile ioport.c once for all targets. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* i386: Drop redundant kvm_enabled testJan Kiszka2009-09-121-2/+1
| | | | | | | cpu_synchronize_state already does this. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Work around OpenSolaris sys/regset.h namespace pollutionBlue Swirl2009-09-121-0/+9
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
OpenPOWER on IntegriCloud