summaryrefslogtreecommitdiffstats
path: root/target-i386/ops_sse.h
Commit message (Collapse)AuthorAgeFilesLines
* target-i386: replace approx_rsqrt and approx_rcp by softfloat opsAurelien Jarno2011-04-251-12/+24
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* softfloat: rename float*_eq() into float*_eq_quiet()Aurelien Jarno2011-04-171-4/+4
| | | | | | | | | | | | | | float*_eq functions have a different semantics than other comparison functions. Fix that by first renaming float*_quiet() into float*_eq_quiet(). Note that it is purely mechanical, and the behaviour should be unchanged. That said it clearly highlight problems due to this different semantics, they are fixed later in this patch series. Cc: Alexander Graf <agraf@suse.de> Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-i386: fix CMPUNORDPS/D and CMPORDPS/D instructionsAurelien Jarno2011-04-171-2/+2
| | | | | | | | SSE instructions CMPUNORDPS/D and CMPORDPS/D do not trigger an invalid exception if operands are qNANs. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-i386: add SSE4a instruction supportAndre Przywara2009-10-041-0/+44
| | | | | | | | | | | | | | This adds support for the AMD Phenom/Barcelona's SSE4a instructions. Those include insertq and extrq, which are doing shift and mask on XMM registers, in two versions (immediate shift/length values and stored in another XMM register). Additionally it implements movntss, movntsd, which are scalar non-temporal stores (avoiding cache trashing). These are implemented as normal stores, though. SSE4a is guarded by the SSE4A CPUID bit (Fn8000_0001:ECX[6]). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Fix Sparse warnings: add "static"Blue Swirl2009-09-051-1/+1
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Update to a hopefully more future proof FSF addressBlue Swirl2009-07-161-2/+1
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Replace gcc variadic macro extension with C99 versionBlue Swirl2009-05-131-2/+2
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Update FSF address in GPL/LGPL boilerplateaurel322009-01-041-1/+1
| | | | | | | | | | The attached patch updates the FSF address in the GPL/LGPL boilerplate in most GPL/LGPLed files, and also in COPYING.LIB. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
* Remove FORCE_RET() and RETURN()aurel322008-12-071-14/+0
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5923 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix pmovsx* / pmovzx* SSE instructions (original fix by Frank Mehnert).balrog2008-12-011-6/+6
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5841 c046a42c-6fe2-441c-8c8c-71466251a162
* target-i386: fix helper_pmovmskb_mmx helperaurel322008-11-161-16/+16
| | | | | | (malc) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5728 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix crc32w decoding, fix a constant width in blendvpd.balrog2008-10-041-1/+1
| | | | | | | | Forced the constant's width to long long so that it doesn't overflow, problem spotted by C. W. Betts. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5417 c046a42c-6fe2-441c-8c8c-71466251a162
* Implement SSE4.1, SSE4.2 (x86).balrog2008-10-041-1/+617
| | | | | | | | This adds support for CPUID_EXT_SSE41, CPUID_EXT_SSE42, CPUID_EXT_POPCNT extensions. Most instructions haven't been tested yet. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5411 c046a42c-6fe2-441c-8c8c-71466251a162
* Implement x86 SSSE3 instructions.balrog2008-09-251-1/+146
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5315 c046a42c-6fe2-441c-8c8c-71466251a162
* converted more helpers to TCG - fixed some SVM issuesbellard2008-05-151-2/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4459 c046a42c-6fe2-441c-8c8c-71466251a162
* converted SSE/MMX ops to TCGbellard2008-05-121-492/+211
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
* 3DNow! instruction set emulationaurel322008-04-081-1/+174
| | | | | | | (Michael Tross) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4180 c046a42c-6fe2-441c-8c8c-71466251a162
* find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the star in ↵ths2007-09-171-2/+2
| | | | | | the regex. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3177 c046a42c-6fe2-441c-8c8c-71466251a162
* find -type f | xargs sed -i 's/[\t ]$//g' # on most filesths2007-09-161-3/+3
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
* fixed movd mmx/sse insnbellard2007-01-161-0/+19
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2321 c046a42c-6fe2-441c-8c8c-71466251a162
* removed switches in op.c (Paul Brook)bellard2005-04-261-68/+14
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1400 c046a42c-6fe2-441c-8c8c-71466251a162
* NaN support in FPU comparisonsbellard2005-03-201-33/+69
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1341 c046a42c-6fe2-441c-8c8c-71466251a162
* soft float supportbellard2005-03-131-63/+63
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1336 c046a42c-6fe2-441c-8c8c-71466251a162
* FORCE_RET() fixes - fpu fixesbellard2005-01-231-21/+29
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1236 c046a42c-6fe2-441c-8c8c-71466251a162
* sse fixbellard2005-01-161-2/+16
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1224 c046a42c-6fe2-441c-8c8c-71466251a162
* MMX/SSE supportbellard2005-01-081-0/+1370
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1205 c046a42c-6fe2-441c-8c8c-71466251a162
OpenPOWER on IntegriCloud