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* target-i386: kvm: save/restore steal time MSRMarcelo Tosatti2013-04-171-0/+21
| | | | | | | | Read and write steal time MSR, so that reporting is functional across migration. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Gleb Natapov <gleb@redhat.com>
* hw: move headers to include/Paolo Bonzini2013-04-081-2/+2
| | | | | | | | | Many of these should be cleaned up with proper qdev-/QOM-ification. Right now there are many catch-all headers in include/hw/ARCH depending on cpu.h, and this makes it necessary to compile these files per-target. However, fixing this does not belong in these patches. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber2013-03-121-1/+1
| | | | | | | | | | Both fields are used in VMState, thus need to be moved together. Explicitly zero them on reset since they were located before breakpoints. Pass PowerPCCPU to kvmppc_handle_halt(). Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-i386: Update VMStateDescription to X86CPUAndreas Färber2013-03-121-108/+107
| | | | | | | | Expose vmstate_cpu as vmstate_x86_cpu and hook it up to CPUClass::vmsd. Adapt opaques and VMState fields to X86CPU. Drop cpu_{save,load}(). Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-i386: Define DR7 bit field constantsliguang2013-01-151-2/+3
| | | | | | | | Implicit use of dr7 bit field is a little hard to understand, so define constants for them and use them consistently. Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* Merge remote-tracking branch 'qemu-kvm/uq/master' into stagingAnthony Liguori2013-01-021-0/+21
|\ | | | | | | | | | | | | | | * qemu-kvm/uq/master: qemu-kvm/pci-assign: 64 bits bar emulation target-i386: Enabling IA32_TSC_ADJUST for QEMU KVM guest VMs Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
| * target-i386: Enabling IA32_TSC_ADJUST for QEMU KVM guest VMsWill Auld2012-12-141-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported Basic design is to emulate the MSR by allowing reads and writes to the hypervisor vcpu specific locations to store the value of the emulated MSRs. In this way the IA32_TSC_ADJUST value will be included in all reads to the TSC MSR whether through rdmsr or rdtsc. As this is a new MSR that the guest may access and modify its value needs to be migrated along with the other MRSs. The changes here are specifically for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added for migrating its value. Signed-off-by: Will Auld <will.auld@intel.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* | softmmu: move include files to include/sysemu/Paolo Bonzini2012-12-191-1/+1
|/ | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* kvm: get/set PV EOI MSRMichael S. Tsirkin2012-08-291-0/+21
| | | | | | | | | Support get/set of new PV EOI MSR, for migration. Add an optional section for MSR value - send it out in case MSR was changed from the default value (0). Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* target-i386: Don't overuse CPUStateAndreas Färber2012-03-141-90/+90
| | | | | | | | | Scripted conversion: sed -i "s/CPUState/CPUX86State/g" target-i386/*.[hc] sed -i "s/#define CPUX86State/#define CPUState/" target-i386/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
* i386: wire up MSR_IA32_MISC_ENABLEAvi Kivity2011-10-241-0/+21
| | | | | | | | | It's needed for its default value - bit 0 specifies that "rep movs" is good enough for memcpy, and Linux may use a slower memcpu if it is not set, depending on cpu family/model. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* kvm: support TSC deadline MSR with subsectionLiu, Jinsong2011-10-241-0/+21
| | | | | | | | | | KVM add emulation of lapic tsc deadline timer for guest. This patch is co-operation work at qemu side. Use subsections to save/restore the field (mtosatti). Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* Revert "kvm: support TSC deadline MSR"Marcelo Tosatti2011-10-241-1/+0
| | | | | | | This reverts commit bfc2455ddbb41148494a084d15777e6bed7533c3. New patch with subsections will follow. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* kvm: support TSC deadline MSRLiu, Jinsong2011-10-031-0/+1
| | | | | | | | KVM add emulation of lapic tsc deadline timer for guest. This patch is co-operation work at qemu side. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* Remove exec-all.h include directivesBlue Swirl2011-06-261-1/+1
| | | | | | Most exec-all.h include directives are now useless, remove them. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* kvm: fix FPU state subsectionMarcelo Tosatti2011-06-211-3/+3
| | | | | | There is no need to specify version on the subsection fields. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* kvm: x86: Save/restore FPU OP, IP and DPJan Kiszka2011-06-191-0/+23
| | | | | | | | | | | | | | | These FPU states are properly maintained by KVM but not yet by TCG. So far we unconditionally set them to 0 in the guest which may cause state corruptions, though not with modern guests. To avoid breaking backward migration, use a conditional subsection that is only written if any of the three fields is non-zero. The guest's FNINIT clears them frequently, and cleared IA32_MISC_ENABLE MSR[2] reduces the probability of non-zero values further so that this subsection is not expected to restrict migration in any common scenario. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Avi Kivity <avi@redhat.com>
* target-i386: remove old code handling float64Aurelien Jarno2011-06-031-101/+0
| | | | | | | | Now that target-i386 uses softfloat, floatx80 is always available and there is no need anymore to have code handling both float64 and floax80. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Revert "x86: Save/restore PAT MSR"Anthony Liguori2011-03-221-2/+0
| | | | | | | | | | | | | This reverts commit c995b495b9d6e60ab1e390bd398a22425d0b3c8c. From Jan Kiszka: Ouch, indeed. Moreover, CPU_SAVE_VERSION was not updated (likely the reason for the breakage). Thanks for debugging this! Anthony (or whoever), please revert this unneeded commit in qemu.git. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: Save/restore PAT MSRJan Kiszka2011-03-161-0/+2
| | | | | Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* Add support for async page fault to qemuGleb Natapov2010-11-161-0/+26
| | | | | | | Add save/restore of MSR for migration and cpuid bit. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* kvm: Enable XSAVE live migration supportSheng Yang2010-06-281-0/+20
| | | | | Signed-off-by: Sheng Yang <sheng@linux.intel.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* KVM: Rework VCPU state writeback APIJan Kiszka2010-03-041-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This grand cleanup drops all reset and vmsave/load related synchronization points in favor of four(!) generic hooks: - cpu_synchronize_all_states in qemu_savevm_state_complete (initial sync from kernel before vmsave) - cpu_synchronize_all_post_init in qemu_loadvm_state (writeback after vmload) - cpu_synchronize_all_post_init in main after machine init - cpu_synchronize_all_post_reset in qemu_system_reset (writeback after system reset) These writeback points + the existing one of VCPU exec after cpu_synchronize_state map on three levels of writeback: - KVM_PUT_RUNTIME_STATE (during runtime, other VCPUs continue to run) - KVM_PUT_RESET_STATE (on synchronous system reset, all VCPUs stopped) - KVM_PUT_FULL_STATE (on init or vmload, all VCPUs stopped as well) This level is passed to the arch-specific VCPU state writing function that will decide which concrete substates need to be written. That way, no writer of load, save or reset functions that interact with in-kernel KVM states will ever have to worry about synchronization again. That also means that a lot of reasons for races, segfaults and deadlocks are eliminated. cpu_synchronize_state remains untouched, just as Anthony suggested. We continue to need it before reading or writing of VCPU states that are also tracked by in-kernel KVM subsystems. Consequently, this patch removes many cpu_synchronize_state calls that are now redundant, just like remaining explicit register syncs. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* Revert "kvm: x86: Save/restore exception_index"Anthony Liguori2009-12-181-1/+0
| | | | | | | | | | | This reverts commit ebbc8a3d8e76d0402f8a08c10c0f32e24715d41d. As suggested by Jan Kiszka, "It was obsoleted by d1793b836f8f123b961c613de1bb1c0c185c84cc and now saves/restores a useless field." Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* kvm: x86: Use separate exception_injected CPUState fieldJan Kiszka2009-12-181-0/+1
| | | | | | | | | Marcelo correctly remarked that there are usage conflicts between QEMU core code and KVM /wrt exception_index. So spend a separate field and also save/restore it properly. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* v2: properly save kvm system time msr registersGlauber Costa2009-12-121-0/+3
| | | | | | | | | | | | | | | | | Currently, the msrs involved in setting up pvclock are not saved over migration and/or save/restore. This patch puts their value in special fields in our CPUState, and deal with them using vmstate. kvm also has to account for it, by including them in the msr list for the ioctls. This is a backport from qemu-kvm.git [v2: sucessfully build without kerneldir ] Signed-off-by: Glauber Costa <glommer@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* kvm: x86: Save/restore exception_indexJan Kiszka2009-12-121-0/+1
| | | | | | | | | | | As KVM now makes use of exception_index to keep pending exceptions, we have to save&restore this field as well. NOTE: We have to nail the arch-independent exception_index down to a certain bit width for proper vmstate processing, namely to 32 bit. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* kvm: x86: Add support for VCPU event statesJan Kiszka2009-12-031-0/+6
| | | | | | | | | This patch extends the qemu-kvm state sync logic with support for KVM_GET/SET_VCPU_EVENTS, giving access to yet missing exception, interrupt and NMI states. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* kvm: x86: Refactor use of interrupt_bitmapJan Kiszka2009-11-171-22/+2
| | | | | | | | | | Drop interrupt_bitmap from the cpustate and solely rely on the integer interupt_injected. This prepares us for the new injected-interrupt interface, which will deprecate the bitmap, while preserving compatibility. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* vmstate: Add version arg to VMSTATE_SINGLE_TEST()Juan Quintela2009-10-271-1/+1
| | | | | | This allows to define VMSTATE_SINGLE with VMSTATE_SINGLE_TEST Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: add 'static' to please SparseBlue Swirl2009-10-181-5/+5
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* x86: fix miss mergeJuan Quintela2009-10-051-1/+2
| | | | | | | | There was a missmerge, and then we got a tail recursive call to cpu_post_load without case base :) Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: port cpu to vmstateJuan Quintela2009-10-051-259/+240
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: factor out cpu_get/put_fpreg()Juan Quintela2009-10-051-72/+137
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: factor out cpu_get/put_mttr_var()Juan Quintela2009-10-051-4/+24
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: factor out cpu_get/put_xmm_reg()Juan Quintela2009-10-051-4/+24
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: factor out cpu_pre/post_load()Juan Quintela2009-10-051-18/+39
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: factor out cpu_pre_save()Juan Quintela2009-10-051-21/+32
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: port segments to vmstateJuan Quintela2009-10-051-8/+16
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: mcg_cap is never 0Juan Quintela2009-10-051-12/+8
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: send mce_banks as an arrayJuan Quintela2009-10-051-10/+4
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: mce_banks always have the same sizeJuan Quintela2009-10-051-2/+2
| | | | | | | | mce_banks is always MCE_BANKS_DEF * 4 in size, value never change CC: Huang Ying <ying.huang@intel.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: add fpregs_format_vmstateJuan Quintela2009-10-051-7/+5
| | | | | | | Don't even ask, being able to load/save between 64<->80bit floats should be forbidden Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: add pending_irq_vmstate to the stateJuan Quintela2009-10-051-9/+7
| | | | | | | It is needed to save the interrupt_bitmap Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: add fptag_vmstate to the stateJuan Quintela2009-10-051-9/+9
| | | | | | | It is needed to store fptags Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: fpus is uint16_t not unsigned intJuan Quintela2009-10-051-8/+8
| | | | | | | We save more that fpus on that 16 bits (fpstt), we need an additional field Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: fpuc is uint16_t not unsigned intJuan Quintela2009-10-051-6/+4
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: make a20_mask int32_tJuan Quintela2009-10-051-7/+2
| | | | | | | | | | This makes the savevm code correct, and sign extensins gives us exactly what we need (namely, sign extend to 64 bits when used with 64bit addresess. Once there, change 0x100000 for 1 << 20, that maks all a20 use the same syntax. Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: hflags is not modified at all, just save it directlyJuan Quintela2009-10-051-8/+3
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* target-i386: add RDTSCP supportAndre Przywara2009-10-041-0/+4
| | | | | | | | | | | | | | RDTSCP reads the time stamp counter and atomically also the content of a 32-bit MSR, which can be freely set by the OS. This allows CPU local data to be queried by userspace. Linux uses this to allow a fast implementation of the getcpu() syscall, which uses the vsyscall page to avoid a context switch. AMD CPUs since K8RevF and Intel CPUs since Nehalem support this instruction. RDTSCP is guarded by the RDTSCP CPUID bit (Fn8000_0001:EDX[27]). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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