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* target-i386: Use mulu2 and muls2Richard Henderson2013-02-271-4/+0
| | | | | | | These correspond very closely to the insns that we're emulating. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-i386: Implement tzcnt and fix lzcntRichard Henderson2013-02-191-3/+2
| | | | | | | | We weren't computing flags for lzcnt at all. At the same time, adjust the implementation of bsf/bsr to avoid the local branch, using movcond instead. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Use clz/ctz for bsf/bsr helpersRichard Henderson2013-02-191-3/+3
| | | | | | And mark the helpers as NO_RWG_SE. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Implement PDEP, PEXTRichard Henderson2013-02-181-0/+3
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Implement MULXRichard Henderson2013-02-181-0/+1
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Use CC_SRC2 for ADC and SBBRichard Henderson2013-02-181-2/+2
| | | | | | | | Add another slot in ENV and store two of the three inputs. This lets us do less work when carry-out is not needed, and avoids the unpredictable CC_OP after translating these insns. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Make helper_cc_compute_{all,c} constRichard Henderson2013-02-181-2/+2
| | | | | | | Pass the data in explicitly, rather than indirectly via env. This avoids all sorts of unnecessary register spillage. Signed-off-by: Richard Henderson <rth@twiddle.net>
* exec: move include files to include/exec/Paolo Bonzini2012-12-191-2/+2
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: rename helper flagsAurelien Jarno2012-10-281-2/+2
| | | | | | | | Rename helper flags to the new ones. This is purely a mechanical change, it's possible to use better flags by looking at the helpers. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* x86: Implement SMEP and SMAPH. Peter Anvin2012-10-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | This patch implements Supervisor Mode Execution Prevention (SMEP) and Supervisor Mode Access Prevention (SMAP) for x86. The purpose of the patch, obviously, is to help kernel developers debug the support for those features. A fair bit of the code relates to the handling of CPUID features. The CPUID code probably would get greatly simplified if all the feature bit words were unified into a single vector object, but in the interest of producing a minimal patch for SMEP/SMAP, and because I had very limited time for this project, I followed the existing style. [ v2: don't change the definition of the qemu64 CPU shorthand, since that breaks loading old snapshots. Per Anthony Liguori this can be fixed once the CPU feature set is snapshot. Change the coding style slightly to conform to checkpatch.pl. ] Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: switch to AREG0 free modeBlue Swirl2012-08-141-4/+4
| | | | | | | | Add an explicit CPUX86State parameter instead of relying on AREG0. Remove temporary wrappers and switch to AREG0 free mode. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* x86: avoid AREG0 in segmentation helpersBlue Swirl2012-08-141-19/+19
| | | | | | | | Add an explicit CPUX86State parameter instead of relying on AREG0. Rename remains of op_helper.c to seg_helper.c. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* x86: avoid AREG0 for misc helpersBlue Swirl2012-08-141-20/+20
| | | | | | Add an explicit CPUX86State parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* x86: avoid AREG0 for SMM helpersBlue Swirl2012-08-141-1/+1
| | | | | | Add an explicit CPUX86State parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* x86: avoid AREG0 for SVM helpersBlue Swirl2012-08-141-11/+11
| | | | | | Add an explicit CPUX86State parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* x86: avoid AREG0 for integer helpersBlue Swirl2012-08-141-25/+25
| | | | | | Add an explicit CPUX86State parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* x86: avoid AREG0 for condition code helpersBlue Swirl2012-08-141-10/+10
| | | | | | Add an explicit CPUX86State parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* x86: avoid AREG0 for FPU helpersBlue Swirl2012-08-141-86/+86
| | | | | | | | | | | Make FPU helpers take a parameter for CPUState instead of relying on global env. Introduce temporary wrappers for FPU load and store ops. Remove wrappers for non-AREG0 code. Don't call unconverted helpers directly. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* x86: avoid AREG0 for exceptionsBlue Swirl2012-06-281-2/+2
| | | | | | | | | | | | Add an explicit CPUX86State parameter instead of relying on AREG0. Merge raise_exception_env() to raise_exception(), likewise with raise_exception_err_env() and raise_exception_err(). Introduce cpu_svm_check_intercept_param() and cpu_vmexit() as wrappers. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-i386: fix SSE rounding and flush to zeroAurelien Jarno2012-01-111-0/+1
| | | | | | | | | | | | SSE rounding and flush to zero control has never been implemented. However given that softfloat-native was using a single state for FPU and SSE and given that glibc is setting both FPU and SSE state in fesetround(), this was working correctly up to the switch to softfloat. Fix that by adding an update_sse_status() function similar to update_fpu_status(), and callin git on write to mxcsr. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-i386: implement lzcnt emulationAndre Przywara2009-10-231-0/+1
| | | | | | | | | | | | | lzcnt is a AMD Phenom/Barcelona added instruction returning the number of leading zero bits in a word. As this is similar to the "bsr" instruction, reuse the existing code. There need to be some more changes, though, as lzcnt always returns a valid value (in opposite to bsr, which has a special case when the operand is 0). lzcnt is guarded by the ABM CPUID bit (Fn8000_0001:ECX_5). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-i386: add RDTSCP supportAndre Przywara2009-10-041-0/+1
| | | | | | | | | | | | | | RDTSCP reads the time stamp counter and atomically also the content of a 32-bit MSR, which can be freely set by the OS. This allows CPU local data to be queried by userspace. Linux uses this to allow a fast implementation of the getcpu() syscall, which uses the vsyscall page to avoid a context switch. AMD CPUs since K8RevF and Intel CPUs since Nehalem support this instruction. RDTSCP is guarded by the RDTSCP CPUID bit (Fn8000_0001:EDX[27]). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* x86: Add support for resume flagJan Kiszka2009-05-221-0/+1
| | | | Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
* TCG variable type checking.pbrook2008-11-171-191/+188
| | | | | | | Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
* SYSENTER/SYSEXIT IA-32e implementation (Alexander Graf).balrog2008-09-251-1/+1
| | | | | | | | | | | On Intel CPUs, sysenter and sysexit are valid in 64-bit mode. This patch makes both 64-bit aware and enables them for Intel CPUs. Add cpu save/load for 64-bit wide sysenter variables. Signed-off-by: Alexander Graf <agraf@suse.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5318 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix some warnings that would be generated by gcc -Wredundant-declsblueswir12008-08-301-1/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
* HLT, MWAIT and MONITOR insn fixes (initial patch by Alexander Graf)bellard2008-06-181-2/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4746 c046a42c-6fe2-441c-8c8c-71466251a162
* reworked SVM interrupt handling logic - fixed vmrun EIP saved value - ↵bellard2008-06-041-4/+1
| | | | | | reworked cr8 handling - added CPUState.hflags2 git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4662 c046a42c-6fe2-441c-8c8c-71466251a162
* 32 bit SVM fixes - INVLPG and INVLPGA updatesbellard2008-06-041-4/+4
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4660 c046a42c-6fe2-441c-8c8c-71466251a162
* SVM reworkbellard2008-05-281-1/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4605 c046a42c-6fe2-441c-8c8c-71466251a162
* proper helper definition registering (all targets must do that)bellard2008-05-221-189/+192
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4530 c046a42c-6fe2-441c-8c8c-71466251a162
* cmpxchg8b fix - added cmpxchg16bbellard2008-05-221-0/+3
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4522 c046a42c-6fe2-441c-8c8c-71466251a162
* convert eflags manipulation insns to TCGbellard2008-05-211-0/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4515 c046a42c-6fe2-441c-8c8c-71466251a162
* converted LSL/LAR/VERW/VERR to TCG - force 16 bit memory access for LSL/LARbellard2008-05-211-4/+4
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4513 c046a42c-6fe2-441c-8c8c-71466251a162
* converted INTO/CMPXCHG8B to TCGbellard2008-05-211-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4510 c046a42c-6fe2-441c-8c8c-71466251a162
* BSR/BSF TCG conversionbellard2008-05-171-0/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4477 c046a42c-6fe2-441c-8c8c-71466251a162
* converted condition code supprot to TCG - converted shift ops to TCGbellard2008-05-171-0/+11
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4470 c046a42c-6fe2-441c-8c8c-71466251a162
* converted more helpers to TCG - fixed some SVM issuesbellard2008-05-151-11/+39
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4459 c046a42c-6fe2-441c-8c8c-71466251a162
* converted more helpers to TCGbellard2008-05-121-2/+73
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4447 c046a42c-6fe2-441c-8c8c-71466251a162
* converted x87 FPU ops to TCGbellard2008-05-121-0/+89
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4444 c046a42c-6fe2-441c-8c8c-71466251a162
* converted SSE/MMX ops to TCGbellard2008-05-121-0/+9
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
* use the TCG code generatorbellard2008-02-011-0/+4
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162
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