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* target-i386: Let cpu_x86_init() return X86CPUAndreas Färber2012-06-041-2/+10
| | | | | | | | Turn cpu_init macro into a static inline function returning CPUX86State for backwards compatibility. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
* target-i386: Pass X86CPU to do_cpu_{init,sipi}()Andreas Färber2012-06-041-2/+2
| | | | | | | Allows to use cpu_reset() in place of cpu_state_reset(). Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
* Expose CPUID leaf 7 only for -cpu hostEduardo Habkost2012-05-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes v2 -> v3; - Check for kvm_enabled() before setting cpuid_7_0_ebx_features Changes v1 -> v2: - Use kvm_arch_get_supported_cpuid() instead of host_cpuid() on cpu_x86_fill_host(). We should use GET_SUPPORTED_CPUID for all bits on "-cpu host" eventually, but I am not changing all the other CPUID leaves because we may not be able to test such an intrusive change in time for 1.1. Description of the bug: Since QEMU 0.15, the CPUID information on CPUID[EAX=7,ECX=0] is being returned unfiltered to the guest, directly from the GET_SUPPORTED_CPUID return value. The problem is that this makes the resulting CPU feature flags unpredictable and dependent on the host CPU and kernel version. This breaks live-migration badly if migrating from a host CPU that supports some features on that CPUID leaf (running a recent kernel) to a kernel or host CPU that doesn't support it. Migration also is incorrect (the virtual CPU changes under the guest's feet) if you migrate in the opposite direction (from an old CPU/kernel to a new CPU/kernel), but with less serious consequences (guests normally query CPUID information only once on boot). Fortunately, the bug affects only users using cpudefs with level >= 7. The right behavior should be to explicitly enable those features on [cpudef] config sections or on the "-cpu" command-line arguments. Right now there is no predefined CPU model on QEMU that has those features: the latest Intel model we have is Sandy Bridge. I would like to get this fixed on 1.1, so I am submitting this patch, that enables those features only if "-cpu host" is being used (as we don't have any pre-defined CPU model that actually have those features). After 1.1 is released, we can make those features properly configurable on [cpudef] and -cpu configuration. One problem is: with this patch, users with the following setup: - Running QEMU 1.0; - Using a cpudef having level >= 7; - Running a kernel that supports the features on CPUID leaf 7; and - Running on a CPU that supports some features on CPUID leaf 7 won't be able to live-migrate to QEMU 1.1. But for these users live-migration is already broken (they can't live-migrate to hosts with older CPUs or older kernels, already), I don't see how to avoid this problem. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* target-i386: Pass X86CPU to cpu_x86_register()Andreas Färber2012-04-251-1/+1
| | | | | | | | Avoids an x86_env_get_cpu() call there, to work with QOM properties. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
* target-i386: QOM'ify CPUAndreas Färber2012-04-101-1/+2
| | | | | | | | | | Embed CPUX86State as first member of X86CPU. Distinguish between "x86_64-cpu" and "i386-cpu". Drop cpu_x86_close() in favor of calling object_delete() directly. For now let CPUClass::reset() call cpu_state_reset(). Signed-off-by: Andreas Färber <afaerber@suse.de>
* Rename CPUState -> CPUArchStateAndreas Färber2012-03-141-1/+1
| | | | | | | | | | | | | Scripted conversion: for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done All occurrences of CPUArchState are expected to be replaced by QOM CPUState, once all targets are QOM'ified and common fields have been extracted. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
* target-i386: Don't overuse CPUStateAndreas Färber2012-03-141-17/+17
| | | | | | | | | Scripted conversion: sed -i "s/CPUState/CPUX86State/g" target-i386/*.[hc] sed -i "s/#define CPUX86State/#define CPUState/" target-i386/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
* target-i386: Mask NX bit from cpu_get_phys_page_debug resultJan Kiszka2012-03-111-0/+1
| | | | | | | | | | | | This was a long pending bug, now revealed by the assert in phys_page_find that stumbled over the large page index returned by cpu_get_phys_page_debug for NX-marked pages: We need to mask out NX and all user-definable bits 52..62 from PDEs and the final PTE to avoid corrupting physical addresses. Reviewed-by: Avi Kivity <avi@redhat.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-i386: Add infrastructure for reporting TPR MMIO accessesJan Kiszka2012-02-181-0/+10
| | | | | | | | | | | | | | | | | This will allow the APIC core to file a TPR access report. Depending on the accelerator and kernel irqchip mode, it will either be delivered right away or queued for later reporting. In TCG mode, we can restart the triggering instruction and can therefore forward the event directly. KVM does not allows us to restart, so we postpone the delivery of events recording in the user space APIC until the current instruction is completed. Note that KVM without in-kernel irqchip will report the address after the instruction that triggered the access. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Avi Kivity <avi@redhat.com>
* kvm: x86: Avoid runtime allocation of xsave bufferJan Kiszka2011-12-221-1/+2
| | | | | | | | Keep a per-VCPU xsave buffer for kvm_put/get_xsave instead of continuously allocating and freeing it on state sync. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* i386: wire up MSR_IA32_MISC_ENABLEAvi Kivity2011-10-241-0/+5
| | | | | | | | | It's needed for its default value - bit 0 specifies that "rep movs" is good enough for memcpy, and Linux may use a slower memcpu if it is not set, depending on cpu family/model. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* kvm: support TSC deadline MSR with subsectionLiu, Jinsong2011-10-241-0/+2
| | | | | | | | | | KVM add emulation of lapic tsc deadline timer for guest. This patch is co-operation work at qemu side. Use subsections to save/restore the field (mtosatti). Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* Revert "kvm: support TSC deadline MSR"Marcelo Tosatti2011-10-241-3/+1
| | | | | | | This reverts commit bfc2455ddbb41148494a084d15777e6bed7533c3. New patch with subsections will follow. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* kvm: support TSC deadline MSRLiu, Jinsong2011-10-031-1/+3
| | | | | | | | KVM add emulation of lapic tsc deadline timer for guest. This patch is co-operation work at qemu side. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* target-i386: Remove data type CCTableStefan Weil2011-09-211-5/+0
| | | | | | | Remove also two assert statements which were the last remaining users. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* Merge remote-tracking branch 'qemu-kvm/uq/master' into stagingAnthony Liguori2011-08-081-0/+1
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| * qemu-x86: Add tsc_freq option to -cpuJoerg Roedel2011-08-051-0/+1
| | | | | | | | | | | | | | | | To let the user configure the desired tsc frequency for the guest if running in KVM. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* | Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl2011-08-071-1/+1
|/ | | | | | | | | Parameter is_softmmu (and its evil mutant twin brother is_softmuu) is not used in cpu_*_handle_mmu_fault() functions, remove them and adjust callers. Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* exec.h cleanupBlue Swirl2011-07-301-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move softmmu_exec.h include directives from target-*/exec.h to target-*/op_helper.c. Move also various other stuff only used in op_helper.c there. Define global env in dyngen-exec.h. For i386, move wrappers for segment and FPU helpers from user-exec.c to op_helper.c. Implement raise_exception_err_env() to handle dynamic CPUState. Move the function declarations to cpu.h since they can be used outside of op_helper.c context. LM32, s390x, UniCore32: remove unused cpu_halted(), regs_to_env() and env_to_regs(). ARM: make raise_exception() static. Convert #include "exec.h" to #include "cpu.h" #include "dyngen-exec.h" and remove now unused target-*/exec.h. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Move cpu_has_work and cpu_pc_from_tb to cpu.hBlue Swirl2011-06-261-0/+47
| | | | | | | Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This is needed by later patches. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* x86: use caller supplied CPUState for interrupt related stuffBlue Swirl2011-06-261-0/+10
| | | | | | | | | | | | | | Several x86 specific functions are called from cpu-exec.c with the assumption that global env register is valid. This will be changed later, so make the functions use caller supplied CPUState parameter. It would be cleaner to move the functions to helper.c, but there are quite a lot of dependencies between do_interrupt() and other functions. Add helpers for svm_check_intercept() and cpu_cc_compute_all() instead of calling the helper (which uses global env, AREG0) directly. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* kvm: x86: Save/restore FPU OP, IP and DPJan Kiszka2011-06-191-0/+4
| | | | | | | | | | | | | | | These FPU states are properly maintained by KVM but not yet by TCG. So far we unconditionally set them to 0 in the guest which may cause state corruptions, though not with modern guests. To avoid breaking backward migration, use a conditional subsection that is only written if any of the three fields is non-zero. The guest's FNINIT clears them frequently, and cleared IA32_MISC_ENABLE MSR[2] reduces the probability of non-zero values further so that this subsection is not expected to restrict migration in any common scenario. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Avi Kivity <avi@redhat.com>
* kvm: Add CPUID support for VIA CPUbrillywu@viatech.com.cn2011-06-141-1/+8
| | | | | | | | | | When KVM is running on VIA CPU with host cpu's model, the feautures of VIA CPU will be passed into kvm guest by calling the CPUID instruction for Centaur. Signed-off-by: BrillyWu<brillywu@viatech.com.cn> Signed-off-by: KaryJin<karyjin@viatech.com.cn> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* target-i386: remove old code handling float64Aurelien Jarno2011-06-031-18/+4
| | | | | | | | Now that target-i386 uses softfloat, floatx80 is always available and there is no need anymore to have code handling both float64 and floax80. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* irq: Privatize CPU_INTERRUPT_NMI.Richard Henderson2011-05-081-0/+1
| | | | | | | | This interrupt name is used by i386, CRIS, and MicroBlaze. Copy the name into each target. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-i386: Privatize some i386-specific interrupt names.Richard Henderson2011-05-081-0/+8
| | | | | | | SMI, VIRQ, INIT, SIPI, and MCE are all only used by the i386 port. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* x86: Properly reset PAT MSRJan Kiszka2011-03-161-2/+2
| | | | | | | | Conforming to the Intel spec, set the power-on value of PAT also on reset, but save it across INIT. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* x86: Optionally avoid injecting AO MCEs while others are pendingJan Kiszka2011-03-151-1/+4
| | | | | | | | | | | | Allow to tell cpu_x86_inject_mce that it should ignore Action Optional MCE events when the target VCPU is still processing another one. This will be used by KVM soon. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> CC: Huang Ying <ying.huang@intel.com> CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> CC: Jin Dongming <jin.dongming@np.css.fujitsu.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* x86: Refine error reporting of MCE injection servicesJan Kiszka2011-03-151-3/+3
| | | | | | | | | | | | | | As this service is used by the human monitor, make sure that errors get reported to the right channel, and also raise the verbosity. This requires to move Monitor typedef in qemu-common.h to resolve the include dependency. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> CC: Huang Ying <ying.huang@intel.com> CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> CC: Jin Dongming <jin.dongming@np.css.fujitsu.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* x86: Small cleanups of MCE helpersJan Kiszka2011-03-151-0/+5
| | | | | | | | | | | Fix some code style issues, use proper headers, and align to cpu_x86 naming scheme. No functional changes. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> CC: Huang Ying <ying.huang@intel.com> CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> CC: Jin Dongming <jin.dongming@np.css.fujitsu.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* x86: Perform implicit mcg_status resetJan Kiszka2011-03-151-1/+2
| | | | | | | | | | Reorder mcg_status in CPUState to achieve automatic clearing on reset. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> CC: Huang Ying <ying.huang@intel.com> CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> CC: Jin Dongming <jin.dongming@np.css.fujitsu.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* kvm: make tsc stable over migration and machine startGlauber Costa2011-02-141-0/+1
| | | | | | | | | | | | | | If the machine is stopped, we should not record two different tsc values upon a save operation. The same problem happens with kvmclock. But kvmclock is taking a different diretion, being now seen as a separate device. Since this is unlikely to happen with the tsc, I am taking the approach here of simply registering a handler for state change, and using a per-CPUState variable that prevents double updates for the TSC. Signed-off-by: Glauber Costa <glommer@redhat.com> CC: Jan Kiszka <jan.kiszka@web.de> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* kvm: x86: Implicitly clear nmi_injected/pending on resetJan Kiszka2011-01-231-2/+4
| | | | | | | | | All CPUX86State variables before CPU_COMMON are automatically cleared on reset. Reorder nmi_injected and nmi_pending to avoid having to touch them explicitly. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* kvm: Improve reporting of fatal errorsJan Kiszka2011-01-231-0/+2
| | | | | | | | | | | | Report KVM_EXIT_UNKNOWN, KVM_EXIT_FAIL_ENTRY, and KVM_EXIT_EXCEPTION with more details to stderr. The latter two are so far x86-only, so move them into the arch-specific handler. Integrate the Intel real mode warning on KVM_EXIT_FAIL_ENTRY that qemu-kvm carries, but actually restrict it to Intel CPUs. Moreover, always dump the CPU state in case we fail. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* Add function for checking mca broadcast of CPUJin Dongming2011-01-211-0/+1
| | | | | | | Add function for checking whether current CPU support mca broadcast. Signed-off-by: Jin Dongming <jin.dongming@np.css.fujitsu.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* target-i386: Fix accidental use of SoftFloat uint64 typeAndreas Färber2010-12-201-4/+4
| | | | | | | | | | | | | | | | softfloat.h's uint64 type has least-width semantics. Use uint64_t instead since that is used in helpers. v4: * Summary change. v3: * Split off. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Acked-by: Huang Ying <ying.huang@intel.com> Acked-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Add support for async page fault to qemuGleb Natapov2010-11-161-0/+1
| | | | | | | Add save/restore of MSR for migration and cpuid bit. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* target-xxx: Use fprintf_function (format checking)Stefan Weil2010-10-301-2/+2
| | | | | | | | | | | | | fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* MCE: Relay UCR MCE to guestMarcelo Tosatti2010-10-201-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Port qemu-kvm's commit 4b62fff1101a7ad77553147717a8bd3bf79df7ef Author: Huang Ying <ying.huang@intel.com> Date: Mon Sep 21 10:43:25 2009 +0800 MCE: Relay UCR MCE to guest UCR (uncorrected recovery) MCE is supported in recent Intel CPUs, where some hardware error such as some memory error can be reported without PCC (processor context corrupted). To recover from such MCE, the corresponding memory will be unmapped, and all processes accessing the memory will be killed via SIGBUS. For KVM, if QEMU/KVM is killed, all guest processes will be killed too. So we relay SIGBUS from host OS to guest system via a UCR MCE injection. Then guest OS can isolate corresponding memory and kill necessary guest processes only. SIGBUS sent to main thread (not VCPU threads) will be broadcast to all VCPU threads as UCR MCE. aliguori: fix build Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Add svm cpuid featuresJoerg Roedel2010-10-201-0/+12
| | | | | | | | | | This patch adds the svm cpuid feature flags to the qemu intialization path. It also adds the svm features available on phenom to its cpu-definition and extends the host cpu type to support all svm features KVM can provide. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Avi Kivity <avi@redhat.com>
* remove exec-all.h inclusion from cpu.hPaolo Bonzini2010-07-031-2/+0
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* move cpu_pc_from_tb to target-*/exec.hPaolo Bonzini2010-07-031-5/+0
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* kvm: Enable XSAVE live migration supportSheng Yang2010-06-281-1/+6
| | | | | Signed-off-by: Sheng Yang <sheng@linux.intel.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* apic: qdev conversion cleanupBlue Swirl2010-06-191-1/+1
| | | | | | | | | Make APICState completely private to apic.c by using DeviceState in external APIs. Move apic_init() to pc.c. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* apic: avoid using CPUState internalsBlue Swirl2010-06-191-11/+16
| | | | | | | | | | | Move the actual CPUState contents handling to cpu.h and cpuid.c. Handle CPU reset and set env->halted in pc.c. Add a function to get the local APIC state of the current CPU for the MMIO. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* apic: avoid passing CPUState from CPU codeBlue Swirl2010-06-191-6/+7
| | | | | | Pass only APICState when accessing APIC from CPU code. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* x86/cpuid: move CPUID functions into separate fileAndre Przywara2010-03-131-3/+6
| | | | | | | | | | | | about half of target-i386/helper.c consist of CPUID related functions. Only one of them is a real TCG helper function. So move the whole CPUID stuff out of this into a separate file to get better maintainable parts. This is only code reordering and should not affect QEMU's functionality. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.Richard Henderson2010-03-121-0/+11
| | | | | | | | | | Removes a set of ifdefs from exec.c. Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other than Alpha. This will be used for page_find_alloc, which is supposed to be using virtual addresses in the first place. Signed-off-by: Richard Henderson <rth@twiddle.net>
* Add cpu model configuration support..john cooper2010-02-221-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a reimplementation of prior versions which adds the ability to define cpu models for contemporary processors. The added models are likewise selected via -cpu <name>, and are intended to displace the existing convention of "-cpu qemu64" augmented with a series of feature flags. A primary motivation was determination of a least common denominator within a given processor class to simplify guest migration. It is still possible to modify an arbitrary model via additional feature flags however the goal here was to make doing so unnecessary in typical usage. The other consideration was providing models names reflective of current processors. Both AMD and Intel have reviewed the models in terms of balancing generality of migration vs. excessive feature downgrade relative to released silicon. This version of the patch replaces the prior hard wired definitions with a configuration file approach for new models. Existing models are thus far left as-is but may easily be transitioned to (or may be overridden by) the configuration file representation. Proposed new model definitions are provided here for current AMD and Intel processors. Each model consists of a name used to select it on the command line (-cpu <name>), and a model_id which corresponds to a least common denominator commercial instance of the processor class. A table of names/model_ids may be queried via "-cpu ?model": : x86 Opteron_G3 AMD Opteron 23xx (Gen 3 Class Opteron) x86 Opteron_G2 AMD Opteron 22xx (Gen 2 Class Opteron) x86 Opteron_G1 AMD Opteron 240 (Gen 1 Class Opteron) x86 Nehalem Intel Core i7 9xx (Nehalem Class Core i7) x86 Penryn Intel Core 2 Duo P9xxx (Penryn Class Core 2) x86 Conroe Intel Celeron_4x0 (Conroe/Merom Class Core 2) : Also added is "-cpu ?dump" which exhaustively outputs all config data for all defined models, and "-cpu ?cpuid" which enumerates all qemu recognized CPUID feature flags. The pseudo cpuid flag 'check' when added to the feature flag list will warn when feature flags (either implicit in a cpu model or explicit on the command line) would have otherwise been quietly unavailable to a guest: # qemu-system-x86_64 ... -cpu Nehalem,check warning: host cpuid 0000_0001 lacks requested flag 'sse4.2|sse4_2' [0x00100000] warning: host cpuid 0000_0001 lacks requested flag 'popcnt' [0x00800000] A similar 'enforce' pseudo flag exists which in addition to the above causes qemu to error exit if requested flags are unavailable. Configuration data for a cpu model resides in the target config file which by default will be installed as: /usr/local/etc/qemu/target-<arch>.conf The format of this file should be self explanatory given the definitions for the above six models and essentially mimics the structure of the static x86_def_t x86_defs. Encoding of cpuid flags names now allows aliases for both the configuration file and the command line which reconciles some Intel/AMD/Linux/Qemu naming differences. This patch was tested relative to qemu.git. Signed-off-by: john cooper <john.cooper@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Add KVM paravirt cpuid leafGleb Natapov2010-01-131-1/+2
| | | | | | | | Initialize KVM paravirt cpuid leaf and allow user to control guest visible PV features through -cpu flag. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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