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* Move cpu_has_work and cpu_pc_from_tb to cpu.hBlue Swirl2011-06-261-0/+47
| | | | | | | Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This is needed by later patches. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* x86: use caller supplied CPUState for interrupt related stuffBlue Swirl2011-06-261-0/+10
| | | | | | | | | | | | | | Several x86 specific functions are called from cpu-exec.c with the assumption that global env register is valid. This will be changed later, so make the functions use caller supplied CPUState parameter. It would be cleaner to move the functions to helper.c, but there are quite a lot of dependencies between do_interrupt() and other functions. Add helpers for svm_check_intercept() and cpu_cc_compute_all() instead of calling the helper (which uses global env, AREG0) directly. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* kvm: x86: Save/restore FPU OP, IP and DPJan Kiszka2011-06-191-0/+4
| | | | | | | | | | | | | | | These FPU states are properly maintained by KVM but not yet by TCG. So far we unconditionally set them to 0 in the guest which may cause state corruptions, though not with modern guests. To avoid breaking backward migration, use a conditional subsection that is only written if any of the three fields is non-zero. The guest's FNINIT clears them frequently, and cleared IA32_MISC_ENABLE MSR[2] reduces the probability of non-zero values further so that this subsection is not expected to restrict migration in any common scenario. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Avi Kivity <avi@redhat.com>
* kvm: Add CPUID support for VIA CPUbrillywu@viatech.com.cn2011-06-141-1/+8
| | | | | | | | | | When KVM is running on VIA CPU with host cpu's model, the feautures of VIA CPU will be passed into kvm guest by calling the CPUID instruction for Centaur. Signed-off-by: BrillyWu<brillywu@viatech.com.cn> Signed-off-by: KaryJin<karyjin@viatech.com.cn> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* target-i386: remove old code handling float64Aurelien Jarno2011-06-031-18/+4
| | | | | | | | Now that target-i386 uses softfloat, floatx80 is always available and there is no need anymore to have code handling both float64 and floax80. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* irq: Privatize CPU_INTERRUPT_NMI.Richard Henderson2011-05-081-0/+1
| | | | | | | | This interrupt name is used by i386, CRIS, and MicroBlaze. Copy the name into each target. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-i386: Privatize some i386-specific interrupt names.Richard Henderson2011-05-081-0/+8
| | | | | | | SMI, VIRQ, INIT, SIPI, and MCE are all only used by the i386 port. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* x86: Properly reset PAT MSRJan Kiszka2011-03-161-2/+2
| | | | | | | | Conforming to the Intel spec, set the power-on value of PAT also on reset, but save it across INIT. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* x86: Optionally avoid injecting AO MCEs while others are pendingJan Kiszka2011-03-151-1/+4
| | | | | | | | | | | | Allow to tell cpu_x86_inject_mce that it should ignore Action Optional MCE events when the target VCPU is still processing another one. This will be used by KVM soon. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> CC: Huang Ying <ying.huang@intel.com> CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> CC: Jin Dongming <jin.dongming@np.css.fujitsu.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* x86: Refine error reporting of MCE injection servicesJan Kiszka2011-03-151-3/+3
| | | | | | | | | | | | | | As this service is used by the human monitor, make sure that errors get reported to the right channel, and also raise the verbosity. This requires to move Monitor typedef in qemu-common.h to resolve the include dependency. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> CC: Huang Ying <ying.huang@intel.com> CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> CC: Jin Dongming <jin.dongming@np.css.fujitsu.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* x86: Small cleanups of MCE helpersJan Kiszka2011-03-151-0/+5
| | | | | | | | | | | Fix some code style issues, use proper headers, and align to cpu_x86 naming scheme. No functional changes. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> CC: Huang Ying <ying.huang@intel.com> CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> CC: Jin Dongming <jin.dongming@np.css.fujitsu.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* x86: Perform implicit mcg_status resetJan Kiszka2011-03-151-1/+2
| | | | | | | | | | Reorder mcg_status in CPUState to achieve automatic clearing on reset. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> CC: Huang Ying <ying.huang@intel.com> CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> CC: Jin Dongming <jin.dongming@np.css.fujitsu.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* kvm: make tsc stable over migration and machine startGlauber Costa2011-02-141-0/+1
| | | | | | | | | | | | | | If the machine is stopped, we should not record two different tsc values upon a save operation. The same problem happens with kvmclock. But kvmclock is taking a different diretion, being now seen as a separate device. Since this is unlikely to happen with the tsc, I am taking the approach here of simply registering a handler for state change, and using a per-CPUState variable that prevents double updates for the TSC. Signed-off-by: Glauber Costa <glommer@redhat.com> CC: Jan Kiszka <jan.kiszka@web.de> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* kvm: x86: Implicitly clear nmi_injected/pending on resetJan Kiszka2011-01-231-2/+4
| | | | | | | | | All CPUX86State variables before CPU_COMMON are automatically cleared on reset. Reorder nmi_injected and nmi_pending to avoid having to touch them explicitly. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* kvm: Improve reporting of fatal errorsJan Kiszka2011-01-231-0/+2
| | | | | | | | | | | | Report KVM_EXIT_UNKNOWN, KVM_EXIT_FAIL_ENTRY, and KVM_EXIT_EXCEPTION with more details to stderr. The latter two are so far x86-only, so move them into the arch-specific handler. Integrate the Intel real mode warning on KVM_EXIT_FAIL_ENTRY that qemu-kvm carries, but actually restrict it to Intel CPUs. Moreover, always dump the CPU state in case we fail. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* Add function for checking mca broadcast of CPUJin Dongming2011-01-211-0/+1
| | | | | | | Add function for checking whether current CPU support mca broadcast. Signed-off-by: Jin Dongming <jin.dongming@np.css.fujitsu.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* target-i386: Fix accidental use of SoftFloat uint64 typeAndreas Färber2010-12-201-4/+4
| | | | | | | | | | | | | | | | softfloat.h's uint64 type has least-width semantics. Use uint64_t instead since that is used in helpers. v4: * Summary change. v3: * Split off. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Acked-by: Huang Ying <ying.huang@intel.com> Acked-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Add support for async page fault to qemuGleb Natapov2010-11-161-0/+1
| | | | | | | Add save/restore of MSR for migration and cpuid bit. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* target-xxx: Use fprintf_function (format checking)Stefan Weil2010-10-301-2/+2
| | | | | | | | | | | | | fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* MCE: Relay UCR MCE to guestMarcelo Tosatti2010-10-201-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Port qemu-kvm's commit 4b62fff1101a7ad77553147717a8bd3bf79df7ef Author: Huang Ying <ying.huang@intel.com> Date: Mon Sep 21 10:43:25 2009 +0800 MCE: Relay UCR MCE to guest UCR (uncorrected recovery) MCE is supported in recent Intel CPUs, where some hardware error such as some memory error can be reported without PCC (processor context corrupted). To recover from such MCE, the corresponding memory will be unmapped, and all processes accessing the memory will be killed via SIGBUS. For KVM, if QEMU/KVM is killed, all guest processes will be killed too. So we relay SIGBUS from host OS to guest system via a UCR MCE injection. Then guest OS can isolate corresponding memory and kill necessary guest processes only. SIGBUS sent to main thread (not VCPU threads) will be broadcast to all VCPU threads as UCR MCE. aliguori: fix build Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Add svm cpuid featuresJoerg Roedel2010-10-201-0/+12
| | | | | | | | | | This patch adds the svm cpuid feature flags to the qemu intialization path. It also adds the svm features available on phenom to its cpu-definition and extends the host cpu type to support all svm features KVM can provide. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Avi Kivity <avi@redhat.com>
* remove exec-all.h inclusion from cpu.hPaolo Bonzini2010-07-031-2/+0
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* move cpu_pc_from_tb to target-*/exec.hPaolo Bonzini2010-07-031-5/+0
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* kvm: Enable XSAVE live migration supportSheng Yang2010-06-281-1/+6
| | | | | Signed-off-by: Sheng Yang <sheng@linux.intel.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* apic: qdev conversion cleanupBlue Swirl2010-06-191-1/+1
| | | | | | | | | Make APICState completely private to apic.c by using DeviceState in external APIs. Move apic_init() to pc.c. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* apic: avoid using CPUState internalsBlue Swirl2010-06-191-11/+16
| | | | | | | | | | | Move the actual CPUState contents handling to cpu.h and cpuid.c. Handle CPU reset and set env->halted in pc.c. Add a function to get the local APIC state of the current CPU for the MMIO. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* apic: avoid passing CPUState from CPU codeBlue Swirl2010-06-191-6/+7
| | | | | | Pass only APICState when accessing APIC from CPU code. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* x86/cpuid: move CPUID functions into separate fileAndre Przywara2010-03-131-3/+6
| | | | | | | | | | | | about half of target-i386/helper.c consist of CPUID related functions. Only one of them is a real TCG helper function. So move the whole CPUID stuff out of this into a separate file to get better maintainable parts. This is only code reordering and should not affect QEMU's functionality. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.Richard Henderson2010-03-121-0/+11
| | | | | | | | | | Removes a set of ifdefs from exec.c. Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other than Alpha. This will be used for page_find_alloc, which is supposed to be using virtual addresses in the first place. Signed-off-by: Richard Henderson <rth@twiddle.net>
* Add cpu model configuration support..john cooper2010-02-221-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a reimplementation of prior versions which adds the ability to define cpu models for contemporary processors. The added models are likewise selected via -cpu <name>, and are intended to displace the existing convention of "-cpu qemu64" augmented with a series of feature flags. A primary motivation was determination of a least common denominator within a given processor class to simplify guest migration. It is still possible to modify an arbitrary model via additional feature flags however the goal here was to make doing so unnecessary in typical usage. The other consideration was providing models names reflective of current processors. Both AMD and Intel have reviewed the models in terms of balancing generality of migration vs. excessive feature downgrade relative to released silicon. This version of the patch replaces the prior hard wired definitions with a configuration file approach for new models. Existing models are thus far left as-is but may easily be transitioned to (or may be overridden by) the configuration file representation. Proposed new model definitions are provided here for current AMD and Intel processors. Each model consists of a name used to select it on the command line (-cpu <name>), and a model_id which corresponds to a least common denominator commercial instance of the processor class. A table of names/model_ids may be queried via "-cpu ?model": : x86 Opteron_G3 AMD Opteron 23xx (Gen 3 Class Opteron) x86 Opteron_G2 AMD Opteron 22xx (Gen 2 Class Opteron) x86 Opteron_G1 AMD Opteron 240 (Gen 1 Class Opteron) x86 Nehalem Intel Core i7 9xx (Nehalem Class Core i7) x86 Penryn Intel Core 2 Duo P9xxx (Penryn Class Core 2) x86 Conroe Intel Celeron_4x0 (Conroe/Merom Class Core 2) : Also added is "-cpu ?dump" which exhaustively outputs all config data for all defined models, and "-cpu ?cpuid" which enumerates all qemu recognized CPUID feature flags. The pseudo cpuid flag 'check' when added to the feature flag list will warn when feature flags (either implicit in a cpu model or explicit on the command line) would have otherwise been quietly unavailable to a guest: # qemu-system-x86_64 ... -cpu Nehalem,check warning: host cpuid 0000_0001 lacks requested flag 'sse4.2|sse4_2' [0x00100000] warning: host cpuid 0000_0001 lacks requested flag 'popcnt' [0x00800000] A similar 'enforce' pseudo flag exists which in addition to the above causes qemu to error exit if requested flags are unavailable. Configuration data for a cpu model resides in the target config file which by default will be installed as: /usr/local/etc/qemu/target-<arch>.conf The format of this file should be self explanatory given the definitions for the above six models and essentially mimics the structure of the static x86_def_t x86_defs. Encoding of cpuid flags names now allows aliases for both the configuration file and the command line which reconciles some Intel/AMD/Linux/Qemu naming differences. This patch was tested relative to qemu.git. Signed-off-by: john cooper <john.cooper@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Add KVM paravirt cpuid leafGleb Natapov2010-01-131-1/+2
| | | | | | | | Initialize KVM paravirt cpuid leaf and allow user to control guest visible PV features through -cpu flag. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* target-i386: Fix evaluation of DR7 registerJan Kiszka2009-12-181-2/+2
| | | | | | | | hw_breakpoint_type and hw_breakpoint_len used the wrong index multiplier to extract type and len. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* kvm: x86: Use separate exception_injected CPUState fieldJan Kiszka2009-12-181-0/+1
| | | | | | | | | Marcelo correctly remarked that there are usage conflicts between QEMU core code and KVM /wrt exception_index. So spend a separate field and also save/restore it properly. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* v2: properly save kvm system time msr registersGlauber Costa2009-12-121-0/+2
| | | | | | | | | | | | | | | | | Currently, the msrs involved in setting up pvclock are not saved over migration and/or save/restore. This patch puts their value in special fields in our CPUState, and deal with them using vmstate. kvm also has to account for it, by including them in the msr list for the ioctls. This is a backport from qemu-kvm.git [v2: sucessfully build without kerneldir ] Signed-off-by: Glauber Costa <glommer@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* kvm: x86: Add support for VCPU event statesJan Kiszka2009-12-031-0/+5
| | | | | | | | | This patch extends the qemu-kvm state sync logic with support for KVM_GET/SET_VCPU_EVENTS, giving access to yet missing exception, interrupt and NMI states. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* kvm: x86: Refactor use of interrupt_bitmapJan Kiszka2009-11-171-2/+1
| | | | | | | | | | Drop interrupt_bitmap from the cpustate and solely rely on the integer interupt_injected. This prepares us for the new injected-interrupt interface, which will deprecate the bitmap, while preserving compatibility. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* target-i386: move recently added vmstate fields at the end of the structureAurelien Jarno2009-10-051-4/+6
| | | | | | | This reduce the impact on hosts that have addressing modes with limited offsets. Suggested by Laurent Desnogues. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* gdbstub: x86: Switch 64/32 bit registers dynamicallyJan Kiszka2009-10-051-2/+5
| | | | | | | | | | | | | | | | | Commit 56aebc891674cd2d07b3f64183415697be200084 changed gdbstub in way that debugging 32 or 16-bit guest code is no longer possible with qemu for x86_64 guest CPUs. Since that commit, qemu only provides registers sets for 64-bit, forcing current and foreseeable gdb to also switch its architecture to 64-bit. And this breaks if the inferior is 32 or 16 bit. No question, this is a gdb issue. But, as it was confirmed in several discusssions with gdb people, it is a non-trivial thing to fix. So until qemu finds a gdb version attach with a rework x86 support, we have to work around it by switching the register layout as the guest switches its execution mode between 16/32 and 64 bit. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: split MTRRVar unionJuan Quintela2009-10-051-4/+6
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: split FPReg unionJuan Quintela2009-10-051-8/+10
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: mce_banks always have the same sizeJuan Quintela2009-10-051-1/+1
| | | | | | | | mce_banks is always MCE_BANKS_DEF * 4 in size, value never change CC: Huang Ying <ying.huang@intel.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: add fpregs_format_vmstateJuan Quintela2009-10-051-0/+1
| | | | | | | Don't even ask, being able to load/save between 64<->80bit floats should be forbidden Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: add pending_irq_vmstate to the stateJuan Quintela2009-10-051-0/+1
| | | | | | | It is needed to save the interrupt_bitmap Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: add fptag_vmstate to the stateJuan Quintela2009-10-051-0/+1
| | | | | | | It is needed to store fptags Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: fpus is uint16_t not unsigned intJuan Quintela2009-10-051-1/+2
| | | | | | | We save more that fpus on that 16 bits (fpstt), we need an additional field Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: fpuc is uint16_t not unsigned intJuan Quintela2009-10-051-1/+1
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: make a20_mask int32_tJuan Quintela2009-10-051-1/+1
| | | | | | | | | | This makes the savevm code correct, and sign extensins gives us exactly what we need (namely, sign extend to 64 bits when used with 64bit addresess. Once there, change 0x100000 for 1 << 20, that maks all a20 use the same syntax. Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* target-i386: add RDTSCP supportAndre Przywara2009-10-041-1/+4
| | | | | | | | | | | | | | RDTSCP reads the time stamp counter and atomically also the content of a 32-bit MSR, which can be freely set by the OS. This allows CPU local data to be queried by userspace. Linux uses this to allow a fast implementation of the getcpu() syscall, which uses the vsyscall page to avoid a context switch. AMD CPUs since K8RevF and Intel CPUs since Nehalem support this instruction. RDTSCP is guarded by the RDTSCP CPUID bit (Fn8000_0001:EDX[27]). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signalNathan Froyd2009-08-241-0/+1
| | | | | | | | | | | | | | | handle_cpu_signal is very nearly copy-paste code for each target, with a few minor variations. This patch sets up appropriate defaults for a generic handle_cpu_signal and provides overrides for particular targets that did things differently. Fixing things like the persistent (XXX: use sigsetjmp) should now become somewhat easier. Previous comments on this patch suggest that the "activate soft MMU for this block" comments refer to defunct functionality. I have removed such blocks for the appropriate targets in this patch. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Unbreak large mem support by removing kqemuAnthony Liguori2009-08-241-14/+0
| | | | | | | | | | | | | | | | | | | | | | kqemu introduces a number of restrictions on the i386 target. The worst is that it prevents large memory from working in the default build. Furthermore, kqemu is fundamentally flawed in a number of ways. It relies on the TSC as a time source which will not be reliable on a multiple processor system in userspace. Since most modern processors are multicore, this severely limits the utility of kqemu. kvm is a viable alternative for people looking to accelerate qemu and has the benefit of being supported by the upstream Linux kernel. If someone can implement work arounds to remove the restrictions introduced by kqemu, I'm happy to avoid and/or revert this patch. N.B. kqemu will still function in the 0.11 series but this patch removes it from the 0.12 series. Paul, please Ack or Nack this patch. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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