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* target-i386: Disable SVM by default in KVM modeEduardo Habkost2014-11-041-0/+1
| | | | | | | | | | | | | | Make SVM be disabled by default on all CPU models when in KVM mode. Nested SVM is enabled by default in the KVM kernel module, but it is probably less stable than nested VMX (which is already disabled by default). Add a new compat function, x86_cpu_compat_kvm_no_autodisable(), to keep compatibility on previous machine-types. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-i386: Rename KVM auto-feature-enable compat functionEduardo Habkost2014-11-031-1/+1
| | | | | | | | | | | The x86_cpu_compat_disable_kvm_features() name was a bit confusing, as it won't forcibly disable the feature for all CPU models (i.e. add it to kvm_default_unset_features), but it will instead turn off the KVM auto-enabling of the feature (i.e. remove it from kvm_default_features), meaning the feature may still be enabled by default in some CPU models). Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-i386: add Intel AVX-512 supportChao Peng2014-10-241-0/+61
| | | | | | | | | Add AVX512 feature bits, register definition and corresponding xsave/vmstate support. Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: update fp status fixPavel Dovgalyuk2014-09-181-0/+2
| | | | | | | | | | | | | | This patch introduces cpu_set_fpuc() function, which changes fpuc field of the CPU state and calls update_fp_status() function. These calls update status of softfloat library and prevent bugs caused by non-coherent rounding settings of the FPU and softfloat. v2 changes: * Added missed calls and intoduced setter function (as suggested by TeLeMan) Reviewed-by: TeLeMan <geleman@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru>
* cpu-exec: Make debug_excp_handler a QOM CPU methodPeter Maydell2014-09-121-1/+1
| | | | | | | Make the debug_excp_handler target specific hook into a QOM CPU method. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* x86: kvm: Add MTRR support for kvm_get|put_msrs()Alex Williamson2014-08-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | The MTRR state in KVM currently runs completely independent of the QEMU state in CPUX86State.mtrr_*. This means that on migration, the target loses MTRR state from the source. Generally that's ok though because KVM ignores it and maps everything as write-back anyway. The exception to this rule is when we have an assigned device and an IOMMU that doesn't promote NoSnoop transactions from that device to be cache coherent. In that case KVM trusts the guest mapping of memory as configured in the MTRR. This patch updates kvm_get|put_msrs() so that we retrieve the actual vCPU MTRR settings and therefore keep CPUX86State synchronized for migration. kvm_put_msrs() is also used on vCPU reset and therefore allows future modificaitons of MTRR state at reset to be realized. Note that the entries array used by both functions was already slightly undersized for holding every possible MSR, so this patch increases it beyond the 28 new entries necessary for MTRR state. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* x86: Use common variable range MTRR countsAlex Williamson2014-08-251-1/+1
| | | | | | | | | | | | We currently define the number of variable range MTRR registers as 8 in the CPUX86State structure and vmstate, but use MSR_MTRRcap_VCNT (also 8) to report to guests the number available. Change this to use MSR_MTRRcap_VCNT consistently. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Support "invariant tsc" flagMarcelo Tosatti2014-06-251-0/+4
| | | | | | | | | | | | | | | | | | | | Expose "Invariant TSC" flag, if KVM is enabled. From Intel documentation: 17.13.1 Invariant TSC The time stamp counter in newer processors may support an enhancement, referred to as invariant TSC. Processor’s support for invariant TSC is indicated by CPUID.80000007H:EDX[8]. The invariant TSC will run at a constant rate in all ACPI P-, C-. and T-states. This is the architectural behavior moving forward. On processors with invariant TSC support, the OS may use the TSC for wall clock timer services (instead of ACPI or HPET timers). TSC reads are much more efficient and do not incur the overhead associated with a ring transition or access to a platform resource. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> [ehabkost: redo feature filtering to use .tcg_features] [ehabkost: add CPUID_APM_INVTSC macro, add it to .unmigratable_flags] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* Merge remote-tracking branch 'remotes/bonzini/softmmu-smap' into stagingPeter Maydell2014-06-051-7/+26
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * remotes/bonzini/softmmu-smap: (33 commits) target-i386: cleanup x86_cpu_get_phys_page_debug target-i386: fix protection bits in the TLB for SMEP target-i386: support long addresses for 4MB pages (PSE-36) target-i386: raise page fault for reserved bits in large pages target-i386: unify reserved bits and NX bit check target-i386: simplify pte/vaddr calculation target-i386: raise page fault for reserved physical address bits target-i386: test reserved PS bit on PML4Es target-i386: set correct error code for reserved bit access target-i386: introduce support for 1 GB pages target-i386: introduce do_check_protect label target-i386: tweak handling of PG_NX_MASK target-i386: commonize checks for PAE and non-PAE target-i386: commonize checks for 4MB and 4KB pages target-i386: commonize checks for 2MB and 4KB pages target-i386: fix coding standards in x86_cpu_handle_mmu_fault target-i386: simplify SMAP handling in MMU_KSMAP_IDX target-i386: fix kernel accesses with SMAP and CPL = 3 target-i386: move check_io helpers to seg_helper.c target-i386: rename KSMAP to KNOSMAP ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-i386: raise page fault for reserved bits in large pagesPaolo Bonzini2014-06-051-0/+2
| | | | | | | | | | | | In large pages, bit 12 is for PAT, but bits starting at 13 are reserved. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target-i386: raise page fault for reserved physical address bitsPaolo Bonzini2014-06-051-0/+10
| | | | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target-i386: simplify SMAP handling in MMU_KSMAP_IDXPaolo Bonzini2014-06-051-1/+1
| | | | | | | | | | | | | | Do not use this MMU index at all if CR4.SMAP is false, and drop the SMAP check from x86_cpu_handle_mmu_fault. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target-i386: fix kernel accesses with SMAP and CPL = 3Paolo Bonzini2014-06-051-4/+11
| | | | | | | | | | | | | | | | | | With SMAP, implicit kernel accesses from user mode always behave as if AC=0. To do this, kernel mode is not anymore a separate MMU mode. Instead, KERNEL_IDX is renamed to KSMAP_IDX and the kernel mode accessors wrap KSMAP_IDX and KNOSMAP_IDX. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target-i386: rename KSMAP to KNOSMAPPaolo Bonzini2014-06-051-3/+3
| | | | | | | | | | | | This is the mode where SMAP is overridden, put "NO" in its name. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | target-i386: set CC_OP to CC_OP_EFLAGS in cpu_load_eflagsPaolo Bonzini2014-05-211-1/+4
| | | | | | | | | | | | | | | | There is no reason to keep that out of the function. The comment refers to the disassembler's cc_op state rather than the CPUState field. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | target-i386: get CPL from SS.DPLPaolo Bonzini2014-05-211-5/+3
|/ | | | | | | | | | | | | | | | | | | CS.RPL is not equal to the CPL in the few instructions between setting CR0.PE and reloading CS. We get this right in the common case, because writes to CR0 do not modify the CPL, but it would not be enough if an SMI comes exactly during that brief period. Were this to happen, the RSM instruction would erroneously set CPL to the low two bits of the real-mode selector; and if they are not 00, the next instruction fetch cannot access the code segment and causes a triple fault. However, SS.DPL *is* always equal to the CPL. In real processors (AMD only) there is a weird case of SYSRET setting SS.DPL=SS.RPL from the STAR register while forcing CPL=3, but we do not emulate that. Tested-by: Kevin O'Connor <kevin@koconnor.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* cpu: make CPU_INTERRUPT_RESET available on all targetsPaolo Bonzini2014-05-131-3/+4
| | | | | | | | | | | | | | | | On the x86, some devices need access to the CPU reset pin (INIT#). Provide a generic service to do this, using one of the internal cpu_interrupt targets. Generalize the PPC-specific code for CPU_INTERRUPT_RESET to other targets. Since PPC does not support migration across QEMU versions (its machine types are not versioned yet), I picked the value that is used on x86, CPU_INTERRUPT_TGT_INT_1. Consequently, TGT_INT_2 and TGT_INT_3 are shifted down by one while keeping their value. Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: preserve FPU and MSR state on INITPaolo Bonzini2014-05-131-16/+26
| | | | | | | | | | | | | | | | | | | Most MSRs, plus the FPU, MMX, MXCSR, XMM and YMM registers should not be zeroed on INIT (Table 9-1 in the Intel SDM). Copy them out of CPUX86State and back in, instead of special casing env->pat. The relevant fields are already consecutive except PAT and SMBASE. However: - KVM and Hyper-V MSRs should be reset because they include memory locations written by the hypervisor. These MSRs are moved together at the end of the preserved area. - SVM state can be moved out of the way since it is written by VMRUN. Cc: Andreas Faerber <afaerber@suse.de> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: fix set of registers zeroed on resetPaolo Bonzini2014-05-131-5/+6
| | | | | | | | | | | | | | | BND0-3, BNDCFGU, BNDCFGS, BNDSTATUS were not zeroed on reset, but they should be (Intel Instruction Set Extensions Programming Reference 319433-015, pages 9-4 and 9-6). Same for YMM. XCR0 should be reset to 1. TSC and TSC_RESET were zeroed already by the memset, remove the explicit assignments. Cc: Andreas Faerber <afaerber@suse.de> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: the x86 CPL is stored in CS.selector - auto update hflags ↵Kevin O'Connor2014-05-131-13/+12
| | | | | | | | | | | | | | | | accordingly. Instead of manually calling cpu_x86_set_cpl() when the CPL changes, check for CPL changes on calls to cpu_x86_load_seg_cache(R_CS). Every location that called cpu_x86_set_cpl() also called cpu_x86_load_seg_cache(R_CS), so cpu_x86_set_cpl() is no longer required. This fixes the SMM handler code as it was not setting/restoring the CPL level manually. Signed-off-by: Kevin O'Connor <kevin@koconnor.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Avoid shifting left into sign bitPeter Maydell2014-03-271-167/+167
| | | | | | | | | | Add 'U' suffixes where necessary to avoid (1 << 31) which shifts left into the sign bit, which is undefined behaviour. Add the suffix also for other constants in the same groupings even if they don't shift into bit 31, for consistency. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-1/+2
| | | | | | | | Most targets were using offsetof(CPUFooState, breakpoints) to determine how much of CPUFooState to clear on reset. Use the next field after CPU_COMMON instead, if any, or sizeof(CPUFooState) otherwise. Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Move watchpoint fields from CPU_COMMON to CPUStateAndreas Färber2014-03-131-1/+1
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber2014-03-131-2/+1
| | | | | | | | Note that while such functions may exist both for *-user and softmmu, only *-user uses the CPUState hook, while softmmu reuses the prototype for calling it directly. Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-i386: Introduce x86_cpu_compat_disable_kvm_features()Eduardo Habkost2014-03-131-2/+2
| | | | | | | | | | Instead of the feature-specific disable_kvm_pv_eoi() function, create a more general function that can be used to disable other feature bits in machine-type compat code. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2014-03-131-14/+0
| | | | | | | | | Default to false. Tidy variable naming and inline cast uses while at it. Tested-by: Jia Liu <proljc@gmail.com> (or32) Signed-off-by: Andreas Färber <afaerber@suse.de>
* Merge remote-tracking branch 'remotes/qmp-unstable/queue/qmp' into stagingPeter Maydell2014-03-041-0/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * remotes/qmp-unstable/queue/qmp: (32 commits) qapi: Add missing null check to opts_start_struct() qapi: Clean up superfluous null check in qapi_dealloc_type_str() qapi: Clean up null checking in generated visitors qapi: Drop unused code in qapi-commands.py qapi: Drop nonsensical header guard in generated qapi-visit.c qapi: Fix licensing of scripts tests/qapi-schema: Cover flat union types tests/qapi-schema: Cover union types with base tests/qapi-schema: Cover complex types with base tests/qapi-schema: Cover anonymous union types tests/qapi-schema: Cover simple argument types tests/qapi-schema: Cover optional command arguments tests/qapi-schema: Actually check successful QMP command response monitor: Remove left-over code in do_info_profile. qerror: Improve QERR_DEVICE_NOT_ACTIVE message qmp: Check for returned data from __json_read in get_events dump: add 'query-dump-guest-memory-capability' command Define the architecture for compressed dump format dump: make kdump-compressed format available for 'dump-guest-memory' dump: add API to write dump pages ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * Define the architecture for compressed dump formatqiaonuohan2014-02-281-0/+2
| | | | | | | | | | | | | | Signed-off-by: Ekaterina Tumanova <tumanova@linux.vnet.ibm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Qiao Nuohan <qiaonuohan@cn.fujitsu.com> Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
* | target-i386: Fix SSE status flag corruptionRichard Henderson2014-02-281-0/+3
|/ | | | | | | | | When we restore the mxcsr register with FXRSTOR, or set it with gdb, we need to update the various SSE status flags in CPUX86State Reported-by: Richard Purdie <richard.purdie@linuxfoundation.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* kvm: add support for hyper-v timersVadim Rozenfeld2014-02-031-0/+1
| | | | | | | | | | http://msdn.microsoft.com/en-us/library/windows/hardware/ff541625%28v=vs.85%29.aspx This code is generic for activating reference time counter or virtual reference time stamp counter Signed-off-by: Vadim Rozenfeld <vrozenfe@redhat.com> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* kvm: make hyperv vapic assist page migratableVadim Rozenfeld2014-02-031-0/+1
| | | | | Signed-off-by: Vadim Rozenfeld <vrozenfe@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* kvm: make hyperv hypercall and guest os id MSRs migratable.Vadim Rozenfeld2014-02-031-0/+2
| | | | | Signed-off-by: Vadim Rozenfeld <vrozenfe@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Merge remote-tracking branch 'qemu-kvm/uq/master' into stagingAnthony Liguori2014-01-241-3/+22
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * qemu-kvm/uq/master: kvm: always update the MPX model specific register KVM: fix addr type for KVM_IOEVENTFD KVM: Retry KVM_CREATE_VM on EINTR mempath prefault: fix off-by-one error kvm: x86: Separately write feature control MSR on reset roms: Flush icache when writing roms to guest memory target-i386: clear guest TSC on reset target-i386: do not special case TSC writeback target-i386: Intel MPX Conflicts: exec.c aliguori: fix trivial merge conflict in exec.c Signed-off-by: Anthony Liguori <aliguori@amazon.com>
| * target-i386: Intel MPXLiu Jinsong2013-12-121-3/+22
| | | | | | | | | | | | | | | | | | Add some MPX related definiation, and hardcode sizes and offsets of xsave features 3 and 4. It also add corresponding part to kvm_get/put_xsave, and vmstate. Signed-off-by: Liu Jinsong <jinsong.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | target-i386: Move apic_state field from CPUX86State to X86CPUChen Fan2013-12-231-4/+0
|/ | | | | | | This motion is preparing for refactoring vCPU APIC subsequently. Signed-off-by: Chen Fan <chen.fan.fnst@cn.fujitsu.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* x86: fix migration from pre-version 12Paolo Bonzini2013-10-021-0/+4
| | | | | | | | | | | | On KVM, the KVM_SET_XSAVE would be executed with a 0 xstate_bv, and not restore anything. Since FP and SSE data are always valid, set them in xstate_bv at reset time. In fact, that value is the same that KVM_GET_XSAVE returns on pre-XSAVE hosts. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Gleb Natapov <gleb@redhat.com>
* Merge remote-tracking branch 'qemu-kvm/uq/master' into stable-1.5Anthony Liguori2013-08-291-78/+103
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * qemu-kvm/uq/master: kvm-stub: fix compilation kvm: shorten the parameter list for get_real_device() kvm: i386: fix LAPIC TSC deadline timer save/restore kvm-all.c: max_cpus should not exceed KVM vcpu limit kvm: Simplify kvm_handle_io kvm: x86: fix setting IA32_FEATURE_CONTROL with nested VMX disabled kvm: add KVM_IRQFD_FLAG_RESAMPLE support kvm: migrate vPMU state target-i386: remove tabs from target-i386/cpu.h Initialize IA32_FEATURE_CONTROL MSR in reset and migration Conflicts: target-i386/cpu.h target-i386/kvm.c aliguori: fixup trivial conflicts due to whitespace and added cpu argument Signed-off-by: Anthony Liguori <anthony@codemonkey.ws>
| * kvm: migrate vPMU statePaolo Bonzini2013-08-091-0/+23
| | | | | | | | | | Reviewed-by: Gleb Natapov <gnatapov@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target-i386: remove tabs from target-i386/cpu.hPaolo Bonzini2013-08-091-96/+96
| | | | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * Initialize IA32_FEATURE_CONTROL MSR in reset and migrationArthur Chunqi Li2013-07-251-0/+2
| | | | | | | | | | | | | | | | | | The recent KVM patch adds IA32_FEATURE_CONTROL support. QEMU needs to clear this MSR when reset vCPU and keep the value of it when migration. This patch add this feature. Signed-off-by: Arthur Chunqi Li <yzt356@gmail.com> Signed-off-by: Gleb Natapov <gleb@redhat.com>
* | target-i386: Move hyperv_* static globals to X86CPUIgor Mammedov2013-08-161-0/+4
|/ | | | | | | | | - since hyperv_* helper functions are used only in target-i386/kvm.c move them there as static helpers Requested-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber2013-07-231-5/+0
| | | | | | | Where no extra implementation is needed, fall back to CPUClass::set_pc(). Acked-by: Michael Walle <michael@walle.cc> (for lm32) Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-i386: Change do_smm_enter() argument to X86CPUAndreas Färber2013-07-091-1/+1
| | | | | | Prepares for log_cpu_state_mask() changing argument to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de>
* linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-userPeter Maydell2013-07-091-9/+0
| | | | | | | | | | | | | The functions cpu_clone_regs() and cpu_set_tls() are not purely CPU related -- they are specific to the TLS ABI for a a particular OS. Move them into the linux-user/ tree where they belong. target-lm32 had entirely unused implementations, since it has no linux-user target; just drop them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-i386/helper: remove DF macroliguang2013-06-151-4/+2
| | | | | | | Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-i386/helper: remove EIP macroliguang2013-06-151-2/+0
| | | | | | | Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-i386/helper: remove EDI macroliguang2013-06-151-2/+0
| | | | | | | Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-i386/helper: remove ESI macroliguang2013-06-151-2/+0
| | | | | | | Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-i386/helper: remove ESP macroliguang2013-06-151-2/+0
| | | | | | | Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-i386/helper: remove EBP macroliguang2013-06-151-2/+0
| | | | | | | Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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