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path: root/target-cris/translate_v10.c
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* target-cris: Move TCG initialization to CRISCPU initfnAndreas Färber2013-02-161-4/+1
| | | | | | | | Split out TCG initialization from cpu_cris_init(). Avoid CPUCRISState dependency for v10-specific initialization and for non-v10 by inlining the decision into the initfn as well. Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-cris: Switch to AREG0 free modeAurelien Jarno2012-09-151-46/+49
| | | | | | | | | Add an explicit CPUCRISState parameter instead of relying on AREG0, and use cpu_ld* in translation and interrupt handling. Remove AREG0 swapping in tlb_fill(). Switch to AREG0 free mode Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-cris: Avoid AREG0 for helpersAurelien Jarno2012-09-151-2/+2
| | | | | | | Add an explicit CPUCRISState parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* cris: Add break support for v10.Edgar E. Iglesias2012-06-141-0/+1
| | | | | | Still no retb Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
* target-cris: Don't overuse CPUStateAndreas Färber2012-03-141-13/+13
| | | | | | | | | Scripted conversion: sed -i "s/CPUState/CPUCRISState/g" target-cris/*.[hc] sed -i "s/#define CPUCRISState/#define CPUState/" target-cris/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
* cris: Handle conditional stores on CRISv10Stefan Sandstrom2011-12-121-6/+66
| | | | | Signed-off-by: Stefan Sandstrom <Stefan.Sandstrom@axis.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* cris: Handle opcode zeroEdgar E. Iglesias2011-06-281-3/+0
| | | | | | It's a valid branch pc + 2. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* Fix typo in comment (truely -> truly)Stefan Weil2011-05-081-1/+1
| | | | | Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* cris: Allow more TB chaining for crisv10Edgar E. Iglesias2011-01-101-4/+6
| | | | Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
* cris: avoid a write only variableBlue Swirl2010-10-131-3/+2
| | | | | | | | | | | Compiling with GCC 4.6.0 20100925 produced a warning: In file included from /src/qemu/target-cris/translate.c:3154:0: /src/qemu/target-cris/translate_v10.c: In function 'dec10_prep_move_m': /src/qemu/target-cris/translate_v10.c:111:22: error: variable 'rd' set but not used [-Werror=unused-but-set-variable] Fix by deleting rd, adjust the only user. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Replace assert(0) with abort() or cpu_abort()Blue Swirl2010-03-181-7/+9
| | | | | | | | | When building with -DNDEBUG, assert(0) will not stop execution so it must not be used for abnormal termination. Use cpu_abort() when in CPU context, abort() otherwise. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Update to a hopefully more future proof FSF addressBlue Swirl2010-03-071-2/+1
| | | | | | | | See also 8167ee883931cb20c6264fc19d040ce2dc6ceaaa, 530e7615ce3c01882e582c84dc6304ab98a3d5c5 and fad6cb1a565bb73f83fc0e2654489457b489e436. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* cris: Mask interrupts on dslots for CRISv10.Edgar E. Iglesias2010-02-201-0/+4
| | | | | | | CRISv10 cores (unlike v32) do not take any interrupts while delayed jumps are pending (delay slots). Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* crisv10: Prettify.Edgar E. Iglesias2010-02-151-95/+91
| | | | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* cris: Add support for CRISv10 translation.Edgar E. Iglesias2010-02-151-0/+1243
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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