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* target-arm: Fix use of free() in cpu_arm_close()Andreas Färber2011-10-201-1/+1
| | | | | | | env is allocated in cpu_arm_init() with g_malloc0(), so free with g_free(). Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm/machine.c: Restore VFP registers correctlyDmitry Koshelev2011-10-191-1/+1
| | | | | | | | | Fix the restoring of VFP registers on vmload. Signed-off-by: Dmitry Koshelev <karaghiozis@gmail.com> Reviewed-by: Juan Quintela <quintela@redhat.com> [peter.maydell: improved commit message a little] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement VFPv4 fused multiply-accumulate insnsPeter Maydell2011-10-194-0/+90
| | | | | | | Implement the fused multiply-accumulate instructions (VFMA, VFMS, VFNMA, VFNMS) which are new in VFPv4. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add ARM UDIV/SDIV supportPeter Maydell2011-10-193-1/+24
| | | | | | | | Add support for UDIV and SDIV in ARM mode. This is a new optional feature for A profile cores (Thumb mode has had UDIV and SDIV for M profile cores for some time). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIVPeter Maydell2011-10-193-4/+5
| | | | | | | | | | Rename the ARM_FEATURE_DIV feature bit to _THUMB_DIV, to make room for a new feature switch enabling DIV in the ARM encoding. (Cores may implement either (a) no divide insns (b) divide insns in Thumb encodings only (c) divide insns in both ARM and Thumb encodings.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: v6 media multiply space: UNDEF on unassigned encodingsPeter Maydell2011-10-191-4/+20
| | | | | | | | Clean up the decoding of the v6 media multiply space so that we UNDEF on unassigned encodings rather than randomly interpreting them as some instruction in this space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* rsqrte_f32: No need to copy sign bit.Christophe LYON2011-10-191-2/+1
| | | | | | | Indeed, the result is known to be always positive. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge remote-tracking branch 'stefanha/trivial-patches' into stagingAnthony Liguori2011-10-101-1/+1
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| * target-arm: Fix typoAndreas Färber2011-10-051-1/+1
| | | | | | | | | | | | | | | | | | The command line option is called -kernel, not -kenrel. Cc: Paul Brook <paul@codesourcery.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* | ARM: fix segfaultBlue Swirl2011-10-081-0/+1
|/ | | | | | | | | Fix a bug in bccd9ec5f098668576342c83d90d6d6833d61d33, target-arm/op_helper.c missed a change unlike all other targets. This lead to a NULL pointer dereferences. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* softmmu_header: pass CPUState to tlb_fillBlue Swirl2011-10-011-4/+2
| | | | | | | Pass CPUState pointer to tlb_fill() instead of architecture local cpu_single_env hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Use glib memory allocation and free functionsAnthony Liguori2011-08-201-1/+1
| | | | | | qemu_malloc/qemu_free no longer exist after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Merge remote-tracking branch 'pm-arm/for-upstream' into pmEdgar E. Iglesias2011-08-093-42/+121
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| * target-arm: Don't print debug messages for various UNDEF casesPeter Maydell2011-07-261-6/+0
| | | | | | | | | | | | | | | | Remove some stray printfs for cases which don't generally happen (some VFP UNDEF cases, reads and writes to unknown cp14 registers); we should simply generate an UNDEF when the instruction is executed. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: UNDEF on a VCVTT/VCVTB UNPREDICTABLE to avoid TCG assertPeter Maydell2011-07-261-8/+11
| | | | | | | | | | | | | | | | | | | | | | VCVTT/VCVTB with bit 8 set is UNPREDICTABLE; we choose to UNDEF. This avoids a TCG assert later when the VCVTT/VCVTB code tries to use a source register that wasn't ever set up. We pull the check for the presence of the half-precision extension up in to this common code as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: Handle UNDEF and UNPREDICTABLE cases for VLDM, VSTMPeter Maydell2011-07-261-7/+31
| | | | | | | | | | | | | | | | Handle the UNDEF and UNPREDICTABLE cases for VLDM and VSTM. In particular, we now generate an undef exception for overlarge imm8 values rather than generating 1000+ TCG ops and hitting an assertion. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: Support v6 barriers in linux-user modePeter Maydell2011-07-261-18/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv6 implemented various operations as special cases of cp15 accesses which are true instructions in v7; this includes barriers (DMB, DSB, ISB). Catch this special case at translate time, so that it works in linux-user mode (which doesn't provide a functional get_cp15 helper) as well as system mode. Includes minor cleanup of the existing cases (single switch statement, and doing the "OK in user mode?" test explicitly rather than hiding it in cp15_user_ok()). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: Mark 1136r1 as a v6K corePeter Maydell2011-07-262-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | The 1136r1 is actually a v6K core (unlike the 1136r0); mark it as such, thus enabling the TLS registers, NOP hints, CLREX, half and byte wide exclusive load/stores, etc. The VA-to-PA translation registers are not present on 1136r1, so introduce a new feature flag for them, which is enabled on 1176, 11MPCore and all v7 cores. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jamie Iles <jamie@jamieiles.com>
| * target-arm: support for ARM1176JZF-s coresJamie Iles2011-07-262-0/+24
| | | | | | | | | | | | | | | | Add support for v6K ARM1176JZF-S. This core includes the VA<->PA translation capability and security extensions. Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: make VMSAv7 remapping and AP dependent on V6KJamie Iles2011-07-261-1/+1
| | | | | | | | | | | | | | | | The VMSAv7 remapping and access permissions were introduced in ARMv6K and not ARMv7. Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl2011-08-073-4/+4
| | | | | | | | | | | | | | | | | | Parameter is_softmmu (and its evil mutant twin brother is_softmuu) is not used in cpu_*_handle_mmu_fault() functions, remove them and adjust callers. Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | exec.h cleanupBlue Swirl2011-07-302-32/+7
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | Move softmmu_exec.h include directives from target-*/exec.h to target-*/op_helper.c. Move also various other stuff only used in op_helper.c there. Define global env in dyngen-exec.h. For i386, move wrappers for segment and FPU helpers from user-exec.c to op_helper.c. Implement raise_exception_err_env() to handle dynamic CPUState. Move the function declarations to cpu.h since they can be used outside of op_helper.c context. LM32, s390x, UniCore32: remove unused cpu_halted(), regs_to_env() and env_to_regs(). ARM: make raise_exception() static. Convert #include "exec.h" to #include "cpu.h" #include "dyngen-exec.h" and remove now unused target-*/exec.h. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Correct spelling of licensedMatthew Fernandez2011-07-232-2/+2
| | | | | | | | | Correct typos of "licenced" to "licensed". Reviewed-by: Stefan Weil <weil@mail.berlios.de> Reviewed-by: Andreas F=E4rber <andreas.faerber@web.de> Signed-off-by: Matthew Fernandez <matthew.fernandez@gmail.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Merge branch 'for-upstream' of git://git.linaro.org/people/pmaydell/qemu-armBlue Swirl2011-07-207-492/+752
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: target-arm: Fix BASEPRI, BASEPRI_MAX, and FAULTMASK access target-arm: Minimal implementation of performance counters Revert "Makefile.target: Allow target helpers to be in any *_helper.c file" Revert "target-arm: Use global env in neon_helper.c helpers" target-arm: Pass fp status pointer explicitly to neon fp helpers target-arm: Make VFP binop helpers take pointer to fpstatus, not CPUState target-arm: Add helper function to generate code to get fpstatus pointer Revert "target-arm: Use global env in iwmmxt_helper.c helpers" Conflicts: Makefile.target
| * target-arm: Fix BASEPRI, BASEPRI_MAX, and FAULTMASK accessSebastian Huber2011-06-221-12/+12
| | | | | | | | | | | | | | | | | | Correct the decode of the register numbers for BASEPRI, BASEPRI_MAX and FAULTMASK, according to "ARMv7-M Architecture Reference Manual" issue D section "B5.2.3 MRS" and "B5.2.3 MSR". Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: Minimal implementation of performance countersPeter Maydell2011-06-224-16/+183
| | | | | | | | | | | | | | | | | | Newer Linux kernels assume the existence of the performance counter cp15 registers. Provide a minimal implementation of these registers. We support no events. This should be compliant with the ARM ARM, except that we don't implement the cycle counter. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * Revert "target-arm: Use global env in neon_helper.c helpers"Peter Maydell2011-06-223-191/+227
| | | | | | | | | | | | | | | | | | This effectively reverts commit 2a3f75b42ac255be09ec2939b96c549ec830efd3 so that we return to passing CPUState to helpers as an explicit parameter. (There were a number of conflicts in target-arm/translate.c which had to be resolved by hand so it is not a pure revert.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: Pass fp status pointer explicitly to neon fp helpersPeter Maydell2011-06-223-74/+113
| | | | | | | | | | | | | | | | | | Make the Neon helpers for various floating point operations take an explicit pointer to the float_status they use, so they don't rely on the global environment pointer any more. This also allows us to drop the mul/sub/add helpers completely and just use the vfp versions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: Make VFP binop helpers take pointer to fpstatus, not CPUStatePeter Maydell2011-06-223-18/+25
| | | | | | | | | | | | | | Make the VFP binop helper functions take a pointer to the fp status, not the entire CPUState. This will allow us to use them for Neon operations too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: Add helper function to generate code to get fpstatus pointerPeter Maydell2011-06-221-24/+16
| | | | | | | | | | | | | | Add and use a helper function which returns a TCGv which is a pointer to the fp_status for either Neon or VFP operations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * Revert "target-arm: Use global env in iwmmxt_helper.c helpers"Peter Maydell2011-06-223-156/+175
| | | | | | | | | | | | | | This reverts commit 947a2fa21b61703802a660a938cabd7b3600ee79, returning the iwmmxt helpers to passing env in as a parameter. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | arm: Add const attribute to some arm_boot_info pointersStefan Weil2011-07-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Parameter 'info' is const, so add the missing attribute. v2: Add 'const' to the local variable info in do_cpu_reset() and to the boot_info field in CPUARMState (suggested by Peter Maydell). Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* | Remove exec-all.h include directivesBlue Swirl2011-06-263-3/+0
| | | | | | | | | | | | Most exec-all.h include directives are now useless, remove them. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | Move cpu_has_work and cpu_pc_from_tb to cpu.hBlue Swirl2011-06-262-12/+13
| | | | | | | | | | | | | | Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This is needed by later patches. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | exec.h: fix coding style and change cpu_has_work to return boolBlue Swirl2011-06-261-3/+3
| | | | | | | | | | | | | | | | | | Before the next patch, fix coding style of the areas affected. Change the type of the return value from cpu_has_work() and qemu_cpu_has_work() to bool. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | cpu_loop_exit: avoid using AREG0Blue Swirl2011-06-261-3/+3
|/ | | | | | | Make cpu_loop_exit() take a parameter for CPUState instead of relying on global env. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-arm: BKPT instructions should raise prefetch aborts with IFSR type 00010Alex Zuepke2011-06-031-0/+1
| | | | | | Signed-off-by: Alex Zuepke <azuepke@sysgo.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Fix compilation failure for 64 bit hostsPeter Maydell2011-06-031-9/+9
| | | | | | | | | Use the correct _ptr aliases for manipulating the pointer to the fp_status; this fixes a compilation failure on 64 bit hosts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm/exec.h: Remove unused #define of M0Peter Maydell2011-05-231-2/+0
| | | | | | | Remove a preprocessor #define which is never used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Signal InvalidOp for Neon GE and GT compares of QNaNPeter Maydell2011-05-231-22/+18
| | | | | | | | | | | | | | | | If the input to a Neon float comparison is a quiet NaN, the ARM ARM specifies that we should raise InvalidOp if the comparison is GE or GT but not for EQ. (Signaling NaNs raise InvalidOp regardless). This means only EQ should use the _quiet version of the comparison function. We implement this by cleaning up the comparison helpers to call the appopriate versions of the softfloat simple comparison functions (float32_le and friends) rather than the generic float32_compare functions. This makes them simple enough that they are clearer opencoded rather than macroised. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Use correct float status for Neon int-float conversionsPeter Maydell2011-05-233-194/+146
| | | | | | | | | | | | | The Neon versions of int-float conversions must use the "standard FPSCR" rather than the default FPSCR. Implement this by having the helper functions take a pointer to the appropriate float_status value rather than simply taking a pointer to the entire CPUState, and making translate.c pass a pointer to vfp.fp_status or vfp.standard_fp_status appropriately for whether the instruction being translated is Neon or VFP. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Signal Underflow when denormal flushed to zero on outputPeter Maydell2011-05-231-1/+1
| | | | | | | | | On ARM the architecture mandates that when an output denormal is flushed to zero we must set the FPSCR UFC (underflow) bit, so map softfloat's float_flag_output_denormal accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Signal InputDenormal for VRECPE, VRSQRTE, VRECPS, VRSQRTSPeter Maydell2011-05-231-0/+12
| | | | | | | | The helpers for VRECPE.F32, VSQRTE.F32, VRECPS and VRSQRTS handle denormals as special cases, so we must set the InputDenormal exception flag ourselves. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Don't set FP exceptions in recip, recip_sqrt estimate fnsPeter Maydell2011-05-231-2/+10
| | | | | | | | | The functions which do the core estimation algorithms for the VRSQRTE and VRECPE instructions should not set floating point exception flags, so use a local fp status for doing these calculations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Fix VMLA, VMLS, VNMLS, VNMLA handling of NaNsPeter Maydell2011-05-151-13/+40
| | | | | | | | | | | Correct handling of NaNs for VFP VMLA, VMLS, VNMLS and VNMLA requires that we implement the set of negations and additions specified by the ARM ARM; plausible looking simplifications like turning (-A + B) into (B - A) or computing (A + B) rather than (B + A) result in selecting the wrong NaN or returning a NaN with the wrong sign bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Merge remote-tracking branch 'stefanha/trivial-patches' into stagingAnthony Liguori2011-05-121-5/+5
|\ | | | | | | | | Conflicts: cpu-all.h
| * Fix typos in comments and code (occured -> occurred and related)Stefan Weil2011-05-081-3/+3
| | | | | | | | | | | | | | The code changed here is an unused data type name (evt_flush_occurred). Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
| * Fix typos in comments (neccessary -> necessary)Stefan Weil2011-05-081-2/+2
| | | | | | | | | | Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* | target-arm: Privatize CPU_INTERRUPT_FIQ.Richard Henderson2011-05-081-0/+4
|/ | | | | | | This interrupt name was only used by the ARM port. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-arm: Don't update base register on abort in Thumb T1 LDMPeter Maydell2011-04-271-3/+14
| | | | | | | | Make sure the base register isn't updated if it is in the load list for a Thumb LDM (T1 encoding) which aborts partway through the load. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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