summaryrefslogtreecommitdiffstats
path: root/target-arm
Commit message (Expand)AuthorAgeFilesLines
* target-arm: Only trap SRS from S-EL1 if specified mode is MONRalf-Philipp Weinmann2019-11-291-1/+2
* target-arm: implement BE32 mode in system emulationPaolo Bonzini2019-11-292-18/+73
* target-arm: implement setendPaolo Bonzini2019-11-293-8/+12
* target-arm: introduce tbflag for endiannessPeter Crosthwaite2019-11-293-2/+9
* target-arm: a64: Add endianness supportPeter Crosthwaite2019-11-291-19/+30
* target-arm: introduce disas flag for endiannessPaolo Bonzini2019-11-293-15/+26
* target-arm: pass DisasContext to gen_aa32_ld*/st*Paolo Bonzini2019-11-291-128/+142
* target-arm: implement SCTLR.EEPeter Crosthwaite2019-11-291-2/+21
* linux-user: arm: handle CPSR.E correctly in strex emulationPaolo Bonzini2019-11-291-0/+11
* arm: cpu: handle BE32 user-mode as BEPeter Crosthwaite2019-11-291-1/+16
* target-arm: cpu: Move cpu_is_big_endian to headerPeter Crosthwaite2019-11-292-16/+22
* target-arm: implement SCTLR.B, drop bswap_codePaolo Bonzini2019-11-297-29/+60
* target-arm: Correct handling of writes to CPSR mode bits from gdb in usermodePeter Maydell2019-11-291-2/+9
* tcg: Add type for vCPU pointersLluís Vilanova2019-11-292-2/+2
* target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEFPeter Maydell2019-11-292-7/+122
* target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAWEdgar E. Iglesias2019-11-291-1/+1
* target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM trapsPeter Maydell2019-11-291-7/+36
* target-arm: Fix handling of SDCR for 32-bit codePeter Maydell2019-11-292-8/+19
* target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1Peter Maydell2019-11-291-0/+10
* target-arm: Make mode switches from Hyp via CPS and MRS illegalPeter Maydell2019-11-291-2/+10
* target-arm: In v8, make illegal AArch32 mode changes set PSTATE.ILPeter Maydell2019-11-291-3/+12
* target-arm: Forbid mode switch to Mon from Secure EL1Peter Maydell2019-11-291-1/+1
* target-arm: Add Hyp mode checks to bad_mode_switch()Peter Maydell2019-11-291-0/+3
* target-arm: Add comment about not implementing NSACR.RFRPeter Maydell2019-11-291-0/+3
* target-arm: In cpsr_write() ignore mode switches from User modePeter Maydell2019-11-291-0/+1
* target-arm: Raw CPSR writes should skip checks and bank switchingPeter Maydell2019-11-294-6/+7
* target-arm: Add write_type argument to cpsr_write()Peter Maydell2019-11-297-10/+20
* target-arm: Give CPSR setting on 32-bit exception return its own helperPeter Maydell2019-11-293-3/+10
* all: Clean up includesPeter Maydell2019-11-292-2/+0
* target-arm: Add PMUSERENR_EL0 registerAlistair Francis2019-11-291-0/+6
* target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registersAlistair Francis2019-11-291-0/+12
* target-arm: Add the pmceid0 and pmceid1 registersAlistair Francis2019-11-294-0/+22
* target-arm: UNDEF in the UNPREDICTABLE SRS-from-System casePeter Maydell2019-11-292-4/+13
* target-arm: Combine user-only and softmmu get/set_r13_banked()Peter Maydell2019-11-291-19/+0
* target-arm: Move bank_number() into internals.hPeter Maydell2019-11-292-26/+25
* target-arm: Move get/set_r13_banked() to op_helper.cPeter Maydell2019-11-292-33/+37
* target-arm: Clean up trap/undef handling of SRSPeter Maydell2019-11-291-5/+61
* target-arm: Report correct syndrome for FPEXC32_EL2 trapsPeter Maydell2019-11-293-2/+20
* target-arm: Implement MDCR_EL3.TDA and MDCR_EL2.TDA trapsPeter Maydell2019-11-291-9/+30
* target-arm: Implement MDCR_EL2.TDRA trapsPeter Maydell2019-11-291-3/+24
* target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA trapsPeter Maydell2019-11-292-1/+34
* target-arm: Fix handling of SCR.SMDPeter Maydell2019-11-291-5/+7
* target-arm: correct CNTFRQ access rightsPeter Maydell2019-11-292-3/+38
* target-arm: Implement checking of fired watchpointSergey Fedorov2019-11-293-14/+25
* target-arm: Fix IL bit reported for Thumb VFP and Neon trapsPeter Maydell2019-11-291-3/+3
* target-arm: Fix IL bit reported for Thumb coprocessor trapsPeter Maydell2019-11-291-4/+4
* target-arm: Correct misleading 'is_thumb' syn_* parameter namesPeter Maydell2019-11-291-14/+14
* target-arm: Enable EL3 for Cortex-A53 and Cortex-A57Peter Maydell2019-11-291-0/+2
* target-arm: Implement NSACR trapping behaviourPeter Maydell2019-11-291-4/+58
* target-arm: Add isread parameter to CPAccessFnsPeter Maydell2019-11-296-37/+68
OpenPOWER on IntegriCloud