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* Merge remote-tracking branch 'rth/tcg-pull' into stagingAnthony Liguori2013-10-112-7/+4
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| * tcg: Remove stray semi-colons from target-*/helper.hRichard Henderson2013-10-101-4/+4
| * tcg: Move helper registration into tcg_context_initRichard Henderson2013-10-101-3/+0
* | Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into stagingAnthony Liguori2013-10-101-3/+0
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| * cpu: Drop cpu_model_str from CPU_COMMONAndreas Färber2013-10-071-3/+0
* | misc: Use new rotate functionsStefan Weil2013-09-251-1/+1
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* target-arm: Add AArch64 gdbstub supportAlexander Graf2013-09-104-1/+80
* target-arm: Add AArch64 translation stubAlexander Graf2013-09-106-4/+178
* target-arm: Prepare translation for AArch64 codeAlexander Graf2013-09-105-38/+151
* target-arm: Disable 32 bit CPUs in 64 bit linux-user buildsPeter Maydell2013-09-101-2/+7
* target-arm: Add new AArch64CPUInfo base class and subclassesPeter Maydell2013-09-103-0/+124
* target-arm: Pass DisasContext* to gen_set_pc_im()Peter Maydell2013-09-101-13/+13
* target-arm: Fix target_ulong/uint32_t confusionsAlexander Graf2013-09-102-6/+7
* target-arm: Export cpu_envAlexander Graf2013-09-102-1/+3
* target-arm: Extract the disas struct to a header fileAlexander Graf2013-09-102-23/+28
* target-arm: Abstract out load/store from a vaddr in AArch32Peter Maydell2013-09-101-124/+210
* target-arm: Implement qmp query-cpu-definitionsCole Robinson2013-09-101-0/+32
* target-arm: fix ARMv7M stack alignment on resetSebastian Ottlik2013-09-101-1/+1
* target-arm: Avoid "1 << 31" undefined behaviourPeter Maydell2013-09-102-18/+18
* target-arm: Use sextract32() in branch decodePeter Maydell2013-09-101-2/+3
* target-arm: Make '-cpu any' available in linux-user mode onlyPeter Maydell2013-09-101-0/+4
* Merge remote-tracking branch 'mjt/trivial-patches' into stagingAnthony Liguori2013-09-031-0/+4
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| * target-arm: Report unimplemented opcodes (LOG_UNIMP)Stefan Weil2013-09-011-0/+4
* | tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson2013-09-021-1/+1
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* aio / timers: Switch entire codebase to the new timer APIAlex Bligh2013-08-222-7/+7
* target-arm: Implement the generic timerPeter Maydell2013-08-205-8/+290
* target-arm: Support coprocessor registers which do I/OPeter Maydell2013-08-202-4/+18
* target-arm: Allow raw_read() and raw_write() to handle 64 bit regsPeter Maydell2013-08-201-2/+10
* target-arm: Make IRQ and FIQ gpio lines on the CPU objectPeter Maydell2013-08-202-0/+63
* target-arm: Implement 'int' loglevelPeter Maydell2013-08-201-0/+42
* cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"Andreas Färber2013-07-291-1/+3
* misc: Use g_assert_not_reached for code which is expected to be unreachableStefan Weil2013-07-271-1/+1
* cpu: Introduce CPUClass::gdb_core_xml_file for GDB_CORE_XMLAndreas Färber2013-07-271-0/+1
* cpu: Introduce CPUClass::gdb_{read,write}_register()Andreas Färber2013-07-274-2/+16
* gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functionsAndreas Färber2013-07-271-3/+3
* target-arm: Move cpu_gdb_{read,write}_register()Andreas Färber2013-07-261-0/+94
* cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regsAndreas Färber2013-07-261-0/+1
* gdbstub: Change gdb_register_coprocessor() argument to CPUStateAndreas Färber2013-07-231-3/+4
* exec: Change cpu_memory_rw_debug() argument to CPUStateAndreas Färber2013-07-231-1/+1
* cpu: Turn cpu_get_phys_page_debug() into a CPUClass hookAndreas Färber2013-07-233-4/+11
* gdbstub: Change syscall callback argument to CPUStateAndreas Färber2013-07-231-2/+6
* cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber2013-07-231-3/+4
* cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber2013-07-231-5/+0
* cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()Andreas Färber2013-07-231-0/+8
* target-arm: Avoid g_hash_table_get_keys()Peter Maydell2013-07-151-2/+10
* target-arm: avoid undefined behaviour when writing TTBCRPeter Maydell2013-07-151-2/+4
* target-arm/helper.c: Allow const opaques in arm CPPeter Crosthwaite2013-07-151-1/+3
* target-arm/helper.c: Implement MIDR aliasesPeter Crosthwaite2013-07-151-5/+11
* target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanupPeter Crosthwaite2013-07-151-9/+4
* target-arm: explicitly decode SEVL instructionMans Rullgard2013-07-151-1/+2
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