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* cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber2014-03-131-1/+1
* cputlb: Change tlb_flush() argument to CPUStateAndreas Färber2014-03-132-11/+30
* cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber2014-03-131-4/+10
* exec: Change cpu_abort() argument to CPUStateAndreas Färber2014-03-132-11/+26
* translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber2014-03-131-1/+1
* cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber2014-03-131-4/+4
* exec: Change tlb_fill() argument to CPUStateAndreas Färber2014-03-131-5/+7
* cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber2014-03-133-5/+5
* cpu: Move opaque field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-4/+5
* cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber2014-03-132-20/+25
* cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber2014-03-134-9/+16
* cpu: Factor out cpu_generic_init()Andreas Färber2014-03-131-13/+1
* cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2014-03-132-6/+7
* target-arm: Clean up ENV_GET_CPU() usageAndreas Färber2014-03-131-5/+7
* target-arm: Implement WFE as a yield operationPeter Maydell2014-03-104-0/+18
* target-arm: Fix intptr_t vs tcg_target_longRichard Henderson2014-03-101-1/+1
* target-arm: Implements the ARM PMCCNTR registerAlistair Francis2014-03-102-4/+89
* target-arm: Fix incorrect setting of E bit in CPSRPeter Maydell2014-03-101-1/+1
* target-arm: Add support for AArch32 ARMv8 CRC32 instructionsWill Newton2014-02-265-0/+100
* target-arm: Add utility function for checking AA32/64 state of an ELPeter Maydell2014-02-261-0/+16
* target-arm: Implement AArch64 view of CPACRPeter Maydell2014-02-262-2/+3
* target-arm: A64: Implement MSR (immediate) instructionsPeter Maydell2014-02-263-1/+51
* target-arm: Store AIF bits in env->pstate for AArch32Peter Maydell2014-02-263-19/+30
* target-arm: A64: Implement WFIPeter Maydell2014-02-261-1/+4
* target-arm: Get MMU index information correct for A64 codePeter Maydell2014-02-262-4/+9
* target-arm: Implement AArch64 OSLAR_EL1 sysreg as WIPeter Maydell2014-02-261-0/+4
* target-arm: Implement AArch64 dummy breakpoint and watchpoint registersPeter Maydell2014-02-262-0/+36
* target-arm: Implement AArch64 ID and feature registersPeter Maydell2014-02-262-0/+55
* target-arm: Implement AArch64 generic timersPeter Maydell2014-02-262-14/+75
* target-arm: Implement AArch64 MPIDRPeter Maydell2014-02-261-2/+4
* target-arm: Implement AArch64 TTBR*Peter Maydell2014-02-262-63/+32
* target-arm: Implement AArch64 VBAR_EL1Peter Maydell2014-02-262-2/+9
* target-arm: Implement AArch64 TCR_EL1Peter Maydell2014-02-262-4/+17
* target-arm: Implement AArch64 SCTLR_EL1Peter Maydell2014-02-262-2/+3
* target-arm: Implement AArch64 memory attribute registersPeter Maydell2014-02-262-1/+26
* target-arm: Implement AArch64 dummy MDSCR_EL1Peter Maydell2014-02-261-0/+6
* target-arm: Implement AArch64 TLB invalidate opsPeter Maydell2014-02-261-0/+73
* target-arm: Implement AArch64 cache invalidate/clean opsPeter Maydell2014-02-262-2/+49
* target-arm: Implement AArch64 MIDR_EL1Peter Maydell2014-02-261-0/+3
* target-arm: Implement AArch64 CurrentEL sysregPeter Maydell2014-02-263-1/+12
* target-arm: A64: Make cache ID registers visible to AArch64Peter Maydell2014-02-264-11/+25
* target-arm: Fix raw read and write functions on AArch64 registersPeter Maydell2014-02-263-3/+15
* arm: vgic device control api supportChristoffer Dall2014-02-262-13/+59
* target-arm: Load correct access bits from ARMv5 level 2 page table descriptorsPeter Maydell2014-02-261-1/+1
* target-arm: Fix incorrect arithmetic constructing short-form PAR for ATS opsPeter Maydell2014-02-261-2/+2
* target-arm: A64: Implement unprivileged load/storePeter Maydell2014-02-201-32/+37
* target-arm: A64: Implement narrowing three-reg-diff operationsPeter Maydell2014-02-201-1/+59
* target-arm: A64: Implement the wide 3-reg-different operationsPeter Maydell2014-02-201-1/+40
* target-arm: A64: Add most remaining three-reg-diff widening opsPeter Maydell2014-02-201-21/+88
* target-arm: A64: Add opcode comments to disas_simd_three_reg_diffPeter Maydell2014-02-201-11/+11
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