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* all: Clean up includesPeter Maydell2019-11-292-2/+0
* target-arm: Add PMUSERENR_EL0 registerAlistair Francis2019-11-291-0/+6
* target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registersAlistair Francis2019-11-291-0/+12
* target-arm: Add the pmceid0 and pmceid1 registersAlistair Francis2019-11-294-0/+22
* target-arm: UNDEF in the UNPREDICTABLE SRS-from-System casePeter Maydell2019-11-292-4/+13
* target-arm: Combine user-only and softmmu get/set_r13_banked()Peter Maydell2019-11-291-19/+0
* target-arm: Move bank_number() into internals.hPeter Maydell2019-11-292-26/+25
* target-arm: Move get/set_r13_banked() to op_helper.cPeter Maydell2019-11-292-33/+37
* target-arm: Clean up trap/undef handling of SRSPeter Maydell2019-11-291-5/+61
* target-arm: Report correct syndrome for FPEXC32_EL2 trapsPeter Maydell2019-11-293-2/+20
* target-arm: Implement MDCR_EL3.TDA and MDCR_EL2.TDA trapsPeter Maydell2019-11-291-9/+30
* target-arm: Implement MDCR_EL2.TDRA trapsPeter Maydell2019-11-291-3/+24
* target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA trapsPeter Maydell2019-11-292-1/+34
* target-arm: Fix handling of SCR.SMDPeter Maydell2019-11-291-5/+7
* target-arm: correct CNTFRQ access rightsPeter Maydell2019-11-292-3/+38
* target-arm: Implement checking of fired watchpointSergey Fedorov2019-11-293-14/+25
* target-arm: Fix IL bit reported for Thumb VFP and Neon trapsPeter Maydell2019-11-291-3/+3
* target-arm: Fix IL bit reported for Thumb coprocessor trapsPeter Maydell2019-11-291-4/+4
* target-arm: Correct misleading 'is_thumb' syn_* parameter namesPeter Maydell2019-11-291-14/+14
* target-arm: Enable EL3 for Cortex-A53 and Cortex-A57Peter Maydell2019-11-291-0/+2
* target-arm: Implement NSACR trapping behaviourPeter Maydell2019-11-291-4/+58
* target-arm: Add isread parameter to CPAccessFnsPeter Maydell2019-11-296-37/+68
* target-arm: Update arm_generate_debug_exceptions() to handle EL2/EL3Peter Maydell2019-11-291-5/+43
* target-arm: Use access_trap_aa32s_el1() for SCR and MVBARPeter Maydell2019-11-291-2/+4
* target-arm: Implement MDCR_EL3 and SDCRPeter Maydell2019-11-292-0/+27
* target-arm: Fix typo in comment in arm_is_secure_below_el3()Peter Maydell2019-11-291-1/+1
* tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson2019-11-292-12/+12
* tcg: Remove lingering references to gen_opc_bufRichard Henderson2019-11-291-2/+1
* target-arm: Don't report presence of EL2 if it doesn't existPeter Maydell2019-11-291-0/+9
* target-arm: Implement the S2 MMU inputsize > pamax checkEdgar E. Iglesias2019-11-291-0/+8
* target-arm: Rename check_s2_startlevel to check_s2_mmu_setupEdgar E. Iglesias2019-11-291-6/+6
* target-arm: Apply S2 MMU startlevel table size check to AArch64Edgar E. Iglesias2019-11-291-8/+8
* target-arm: Make various system registers visible to EL3Peter Maydell2019-11-291-29/+29
* log: do not unnecessarily include qom/cpu.hPaolo Bonzini2019-11-292-0/+2
* arm: Clean up includesPeter Maydell2019-11-291-0/+1
* gdb: provide the name of the architecture in the target.xmlDavid Hildenbrand2019-11-292-0/+18
* target-arm: Implement FPEXC32_EL2 system registerPeter Maydell2019-11-291-0/+16
* target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM modePeter Maydell2019-11-291-1/+5
* target-arm: Implement remaining illegal return event checksPeter Maydell2019-11-291-0/+10
* target-arm: Handle exception return from AArch64 to non-EL0 AArch32Peter Maydell2019-11-291-21/+59
* target-arm: Fix wrong AArch64 entry offset for EL2/EL3 targetPeter Maydell2019-11-291-1/+20
* target-arm: Pull semihosting handling out to arm_cpu_do_interrupt()Peter Maydell2019-11-291-39/+81
* target-arm: Use a single entry point for AArch64 and AArch32 exceptionsPeter Maydell2019-11-293-36/+44
* target-arm: Move aarch64_cpu_do_interrupt() to helper.cPeter Maydell2019-11-293-105/+101
* target-arm: Properly support EL2 and EL3 in arm_el_is_aa64()Peter Maydell2019-11-291-9/+24
* target-arm: Support multiple address spaces in page table walksPeter Maydell2019-11-292-2/+15
* target-arm: Implement cpu_get_phys_page_attrs_debugPeter Maydell2019-11-293-6/+8
* target-arm: Implement asidx_from_attrsPeter Maydell2019-11-292-0/+9
* target-arm: Add QOM property for Secure memory regionPeter Maydell2019-11-293-0/+41
* target-arm: Clean up includesPeter Maydell2019-11-2919-31/+19
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