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* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2015-10-191-1/+1
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| * kvm: Pass PCI device pointer to MSI routing functionsPavel Fedin2015-10-191-1/+1
* | target-arm: Fix CPU breakpoint handlingSergey Fedorov2015-10-164-21/+46
* | target-arm: Fix GDB breakpoint handlingSergey Fedorov2015-10-161-0/+6
* | target-arm: implement arm_debug_target_el()Sergey Fedorov2015-10-161-1/+16
* | target-arm: Add MDCR_EL2Sergey Fedorov2015-10-162-0/+13
* | target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregsDavorin Mista2015-10-162-2/+24
* | target-arm: Avoid calling arm_el_is_aa64() function for unimplemented ELSergey Sorokin2015-10-162-5/+21
* | target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin2015-10-163-4/+27
* | target-arm: Add missing 'static' attributeStefan Weil2015-10-161-1/+1
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* qdev: Protect device-list-properties against broken devicesMarkus Armbruster2015-10-091-0/+11
* tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-073-78/+14
* tcg: Pass data argument to restore_state_to_opcRichard Henderson2015-10-071-4/+5
* tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-072-1/+8
* target-*: Drop cpu_gen_code defineRichard Henderson2015-10-071-1/+0
* target-arm: Add condexec state to insn_startRichard Henderson2015-10-073-2/+4
* target-*: Introduce and use cpu_breakpoint_testRichard Henderson2015-10-072-28/+29
* target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson2015-10-072-6/+7
* target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson2015-10-072-8/+2
* tcg: Rename debug_insn_start to insn_startRichard Henderson2015-10-072-2/+2
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2015-09-251-2/+0
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| * arm: Remove ELF_MACHINE from cpu.hPeter Crosthwaite2015-09-251-2/+0
* | arm: clarify the use of muldiv64()Laurent Vivier2015-09-251-6/+8
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* hw/intc: Initial implementation of vGICv3Pavel Fedin2015-09-242-0/+28
* arm_kvm: Do not assume particular GIC type in kvm_arch_irqchip_create()Pavel Fedin2015-09-242-7/+21
* target-arm: Use new revbit functionsRichard Henderson2015-09-152-25/+2
* target-arm: Add VMPIDR_EL2Edgar E. Iglesias2015-09-142-2/+25
* target-arm: Break out mpidr_read_val()Edgar E. Iglesias2015-09-141-1/+6
* target-arm: Add VPIDR_EL2Edgar E. Iglesias2015-09-142-1/+42
* target-arm: Suppress EPD for S2, EL2 and EL3 translationsEdgar E. Iglesias2015-09-141-2/+4
* target-arm: Suppress TBI for S2 translationsEdgar E. Iglesias2015-09-141-1/+3
* target-arm: Add VTTBR_EL2Edgar E. Iglesias2015-09-142-2/+33
* target-arm: Add VTCR_EL2Edgar E. Iglesias2015-09-142-2/+42
* target-arm: Use tcg_gen_extrh_i64_i32Richard Henderson2015-09-141-25/+9
* target-arm: Recognize RORRichard Henderson2015-09-141-12/+21
* target-arm: Eliminate unnecessary zero-extend in disas_bitfieldRichard Henderson2015-09-141-1/+5
* target-arm: Recognize UXTB, UXTH, LSR, LSLRichard Henderson2015-09-141-0/+17
* target-arm: Recognize SXTB, SXTH, SXTW, ASRRichard Henderson2015-09-141-1/+23
* target-arm: Implement fcsel with movcondRichard Henderson2015-09-141-28/+17
* target-arm: Implement ccmp branchlessRichard Henderson2015-09-141-16/+58
* target-arm: Use setcond and movcond for cselRichard Henderson2015-09-141-36/+49
* target-arm: Handle always condition codes within arm_test_ccRichard Henderson2015-09-141-0/+9
* target-arm: Introduce DisasCompareRichard Henderson2015-09-142-46/+78
* target-arm: Share all common TCG temporariesRichard Henderson2015-09-143-27/+13
* tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt2015-09-112-4/+4
* typofixes - v4Veres Lajos2015-09-111-2/+2
* maint: remove / fix many doubled wordsDaniel P. Berrange2015-09-113-4/+4
* target-arm: Add AArch64 access to PAR_EL1Edgar E. Iglesias2015-09-081-0/+6
* target-arm: Correct opc1 for AT_S12ExxEdgar E. Iglesias2015-09-081-4/+4
* target-arm: Log the target EL when taking exceptionsEdgar E. Iglesias2015-09-081-1/+2
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