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* target-arm: BKPT instructions should raise prefetch aborts with IFSR type 00010Alex Zuepke2011-06-031-0/+1
| | | | | | Signed-off-by: Alex Zuepke <azuepke@sysgo.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Fix compilation failure for 64 bit hostsPeter Maydell2011-06-031-9/+9
| | | | | | | | | Use the correct _ptr aliases for manipulating the pointer to the fp_status; this fixes a compilation failure on 64 bit hosts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm/exec.h: Remove unused #define of M0Peter Maydell2011-05-231-2/+0
| | | | | | | Remove a preprocessor #define which is never used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Signal InvalidOp for Neon GE and GT compares of QNaNPeter Maydell2011-05-231-22/+18
| | | | | | | | | | | | | | | | If the input to a Neon float comparison is a quiet NaN, the ARM ARM specifies that we should raise InvalidOp if the comparison is GE or GT but not for EQ. (Signaling NaNs raise InvalidOp regardless). This means only EQ should use the _quiet version of the comparison function. We implement this by cleaning up the comparison helpers to call the appopriate versions of the softfloat simple comparison functions (float32_le and friends) rather than the generic float32_compare functions. This makes them simple enough that they are clearer opencoded rather than macroised. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Use correct float status for Neon int-float conversionsPeter Maydell2011-05-233-194/+146
| | | | | | | | | | | | | The Neon versions of int-float conversions must use the "standard FPSCR" rather than the default FPSCR. Implement this by having the helper functions take a pointer to the appropriate float_status value rather than simply taking a pointer to the entire CPUState, and making translate.c pass a pointer to vfp.fp_status or vfp.standard_fp_status appropriately for whether the instruction being translated is Neon or VFP. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Signal Underflow when denormal flushed to zero on outputPeter Maydell2011-05-231-1/+1
| | | | | | | | | On ARM the architecture mandates that when an output denormal is flushed to zero we must set the FPSCR UFC (underflow) bit, so map softfloat's float_flag_output_denormal accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Signal InputDenormal for VRECPE, VRSQRTE, VRECPS, VRSQRTSPeter Maydell2011-05-231-0/+12
| | | | | | | | The helpers for VRECPE.F32, VSQRTE.F32, VRECPS and VRSQRTS handle denormals as special cases, so we must set the InputDenormal exception flag ourselves. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Don't set FP exceptions in recip, recip_sqrt estimate fnsPeter Maydell2011-05-231-2/+10
| | | | | | | | | The functions which do the core estimation algorithms for the VRSQRTE and VRECPE instructions should not set floating point exception flags, so use a local fp status for doing these calculations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Fix VMLA, VMLS, VNMLS, VNMLA handling of NaNsPeter Maydell2011-05-151-13/+40
| | | | | | | | | | | Correct handling of NaNs for VFP VMLA, VMLS, VNMLS and VNMLA requires that we implement the set of negations and additions specified by the ARM ARM; plausible looking simplifications like turning (-A + B) into (B - A) or computing (A + B) rather than (B + A) result in selecting the wrong NaN or returning a NaN with the wrong sign bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Merge remote-tracking branch 'stefanha/trivial-patches' into stagingAnthony Liguori2011-05-121-5/+5
|\ | | | | | | | | Conflicts: cpu-all.h
| * Fix typos in comments and code (occured -> occurred and related)Stefan Weil2011-05-081-3/+3
| | | | | | | | | | | | | | The code changed here is an unused data type name (evt_flush_occurred). Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
| * Fix typos in comments (neccessary -> necessary)Stefan Weil2011-05-081-2/+2
| | | | | | | | | | Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* | target-arm: Privatize CPU_INTERRUPT_FIQ.Richard Henderson2011-05-081-0/+4
|/ | | | | | | This interrupt name was only used by the ARM port. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-arm: Don't update base register on abort in Thumb T1 LDMPeter Maydell2011-04-271-3/+14
| | | | | | | | Make sure the base register isn't updated if it is in the load list for a Thumb LDM (T1 encoding) which aborts partway through the load. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: fix LDMIA bug on page boundaryYuYeon Oh2011-04-271-1/+9
| | | | | | | | | | | | target-arm: fix LDMIA bug on page boundary When consecutive memory locations are on page boundary, a base register may be loaded before page fault occurs. After page fault handling, it losts the memory location information. To solve this problem, loading a base register has to put back. Signed-off-by: Yuyeon Oh <yuyeon.oh@samsung.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Handle UNDEF cases for Neon VLD/VST multiple-structuresPeter Maydell2011-04-251-0/+15
| | | | | | | | Correctly UNDEF for Neon VLD/VST "multiple structures" forms where the align field is not valid. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Handle UNDEFs for Neon single element load/storesPeter Maydell2011-04-251-0/+34
| | | | | | | | Handle the UNDEF and UNPREDICTABLE cases for Neon "single element to one lane" VLD and "single element from one lane" VST. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Set Invalid flag for NaN in float-to-int conversionsPeter Maydell2011-04-201-0/+9
| | | | | | | | | When we catch the special case of an input NaN in ARM float to int helper functions, set the Invalid flag as well as returning the correct result. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Implement basic part of SA-1110/SA-1100Dmitry Eremin-Solenikov2011-04-202-0/+12
| | | | | | | | | | | | | | | | | Basic implementation of DEC/Intel SA-1100/SA-1110 chips emulation. Implemented: - IRQs - GPIO - PPC - RTC - UARTs (no IrDA/etc.) - OST reused from pxa25x Everything else is TODO (esp. PM/idle/sleep!) - see the todo in the hw/strongarm.c Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Remove unused function parameter from cpu_restore_stateStefan Weil2011-04-201-1/+1
| | | | | | | | | The previous patch removed the need for parameter puc. Is is now unused, so remove it. Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
* Remove unused function parameters from gen_pc_load and rename the functionStefan Weil2011-04-201-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Function gen_pc_load was introduced in commit d2856f1ad4c259e5766847c49acbb4e390731bd4. The only reason for parameter searched_pc was a debug statement in target-i386/translate.c. Parameter puc was needed by target-sparc until commit d7da2a10402f1644128b66414ca8f86bdea9ae7c. Remove searched_pc from the debug statement and remove both parameters from the parameter list of gen_pc_load. As the function name gen_pc_load was also misleading, it is now called restore_state_to_opc. This new name was suggested by Peter Maydell, thanks. v2: Remove last parameter, too, and rename the function. v3: Fix [] typo in target-arm/translate.c. Fix wrong SHA1 object name in commit message (copy+paste error). Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
* move helpers.h to helper.hLluís2011-04-176-7/+7
| | | | | | | This provides a consistent naming scheme across all targets. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Fix some typos in comments and documentationStefan Weil2011-04-161-1/+1
| | | | | | | | | | | helpfull -> helpful usefull -> useful cotrol -> control and a grammar fix. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* target-arm: Don't overflow when calculating value for signed VABALPeter Maydell2011-04-131-17/+21
| | | | | | | | | | In the VABAL instruction we take the absolute difference of two values of size x and store it in a result of size 2x. This means we have to be careful to calculate the absolute difference using a wide enough type that we don't accidentally overflow. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Detect tininess before rounding for FP operationsPeter Maydell2011-04-121-0/+4
| | | | | | | | The ARM architecture mandates that we detect tininess before rounding, so set the softfloat fp_status up appropriately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Handle UNDEF cases for VDUP (scalar)Juha Riihimäki2011-04-121-0/+3
| | | | | | | | | | Handle the UNDEF cases for VDUP(scalar): imm4 == x000 Q == 1 && Vd<0> == 1 Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Treat UNPREDICTABLE VTBL, VTBX case as UNDEFPeter Maydell2011-04-121-1/+8
| | | | | | | | | Catch the UNPREDICTABLE case for Neon VTBL,VTBX, and UNDEF it rather than allowing the helper function to index off the end of the register file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Handle UNDEF cases for Neon 2 register misc formsPeter Maydell2011-04-121-5/+16
| | | | | | | | | | | | | Add missing UNDEF checks for Neon "two register miscellaneous" forms: * all instructions except VMOVN,VQMOVN must UNDEF if Q==1 && (Vd<0> == 1 || Vm<0> == 1) * VMOVN,VQMOVN,VCVT.F16.F32 UNDEF if Q == 1 || Vm<0> == 1 * VSHLL,VCVT.F32.F16 UNDEF if Q == 1 || Vd<0> == 1 (The only other UNDEF case is VZIP,VUZP if Q == 0 && size == 10, which we already handle.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Simplify checking of size field in Neon 2reg-misc formsPeter Maydell2011-04-121-76/+179
| | | | | | | | | | | Many of the Neon "2 register misc" instruction forms require invalid size fields to cause the instruction to UNDEF. Pull this information out into an array; this simplifies the code and also means we can do the check early and avoid the problem of leaking TCG temporaries in the illegal_op case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Handle UNDEF cases for VEXTPeter Maydell2011-04-121-0/+4
| | | | | | | VEXT must UNDEF if Q == 1 && (Vd<0> == 1 || Vr<0> == 1 || Vm<0> == 1) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Handle UNDEF cases for Neon 2 regs + scalar formsPeter Maydell2011-04-121-10/+27
| | | | | | | | Add missing checks for cases which must UNDEF in the Neon "2 registers and a scalar" data processing instruction space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Handle UNDEF cases for Neon 3-regs-different-widthsPeter Maydell2011-04-121-20/+36
| | | | | | | | Add missing UNDEF checks for instructions in the Neon "3 registers of different widths" data processing space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Handle UNDEF cases for Neon invalid modified-immediatesPeter Maydell2011-04-121-0/+10
| | | | | | | | | | For Neon "one register and a modified immediate value" forms, the combination op=1 cmode=1111 is unallocated and should UNDEF. All instructions of this form also UNDEF if Q == 1 and Vd<0> == 1. We also add a comment on the only UNPREDICTABLE in this space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Collapse VSRI case into VSHL, VSLIPeter Maydell2011-04-121-4/+0
| | | | | | | | | | | Collapse some switch cases for VSRI into those for VSHL, VSLI, since the bodies are the same. (This is not completely obvious for the size < 3 case, but since for VSRI we know U=1 the GEN_NEON_INTEGER_OP() expansion is equivalent to the open-coded VSHL/VSLI case.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Handle UNDEF cases for Neon "2 regs and shift" insnsPeter Maydell2011-04-121-19/+22
| | | | | | | | | Correctly handle all the UNDEF cases for Neon instructions of the "2 registers and shift" form, and make sure that we check for these cases early enough not to leak TCG temporaries. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Simplify three-register pairwise codeJuha Riihimäki2011-04-121-11/+8
| | | | | | | | | | Since we know that the case of (pairwise && q) has been caught earlier, we can simplify the register setup code for each pass in the three-register-same-size Neon loop. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Handle UNDEF cases for Neon 3-regs-same insnsPeter Maydell2011-04-121-11/+43
| | | | | | | | | Correct the handling of UNDEF cases for the NEON "3 registers same size" forms, by adding missing checks and rationalising some others so they are done early enough to avoid leaking TCG temporaries. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Use lookup table for size check on Neon 3-reg-same insnsPeter Maydell2011-04-121-64/+133
| | | | | | | | | | | | Simplify the checks for invalid size values for the Neon "three registers of the same size" instruction forms (and add them where they were missing) by using a lookup table. This includes adding symbolic constants for the op values in this space, since we now use them in multiple places. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* arm: basic support for ARMv4/ARMv4T emulationDmitry Eremin-Solenikov2011-04-103-12/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently target-arm/ assumes at least ARMv5 core. Add support for handling also ARMv4/ARMv4T. This changes the following instructions: BX(v4T and later) BKPT, BLX, CDP2, CLZ, LDC2, LDRD, MCRR, MCRR2, MRRC, MCRR, MRC2, MRRC, MRRC2, PLD QADD, QDADD, QDSUB, QSUB, STRD, SMLAxy, SMLALxy, SMLAWxy, SMULxy, SMULWxy, STC2 (v5 and later) All instructions that are "v5TE and later" are also bound to just v5, as that's how it was before. This patch doesn _not_ include disabling of cp15 access and base-updated data abort model (that will be required to emulate chips based on a ARM7TDMI), because: * no ARM7TDMI chips are currently emulated (or planned) * those features aren't strictly necessary for my purposes (SA-1 core emulation). All v5 models are handled as they are v5T. Internally we still have a check if the model is a v5(T) or v5TE, but as all emulated cores are v5TE, those two cases are simply aliased (for now). Patch is heavily based on patch by Filip Navara <filip.navara@gmail.com> which in turn is based on work by Ulrich Hecht <uli@suse.de> and Vincent Sanders <vince@kyllikki.org>. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Fix conversions from pointer to tcg_target_longStefan Weil2011-04-101-1/+1
| | | | | | | | | | | | tcg_gen_exit_tb takes a parameter of type tcg_target_long, so the type casts of pointer to long should be replaced by type casts of pointer to tcg_target_long (suggested by Blue Swirl). These changes are needed for build environments where sizeof(long) != sizeof(void *), especially for w64. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Make Neon helper routines use correct FP statusPeter Maydell2011-04-041-2/+1
| | | | | | | | | | Make the Neon helper routines use the correct FP status from the CPUEnv rather than using a dummy static one. This means they will correctly handle denormals and NaNs and will set FPSCR exception bits properly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Use global env in iwmmxt_helper.c helpersPeter Maydell2011-04-043-175/+156
| | | | | | | | Use the global 'env' variable in the helper functions in iwmmxt_helper.c. This means we don't need to pass env as an argument to them any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Use global env in neon_helper.c helpersPeter Maydell2011-04-043-206/+191
| | | | | | | | Use the global 'env' variable in the helper functions in neon_helper.c. This means we don't need to pass env as an argument to them any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm/helper.c: For float-int conversion helpers pass ints as intsPeter Maydell2011-04-032-130/+85
| | | | | | | | | | | | Correct the argument and return types for the float<->int conversion helper functions so that integer arguments and return values are declared as uint32_t/uint64_t, not float32/float64. This allows us to remove the hand-rolled functions which were doing bitwise copies between the types via unions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Use new softfloat min/max functions for VMAX, VMINPeter Maydell2011-04-031-6/+2
| | | | | | | | | Use the new softfloat min/max functions to implement the Neon VMAX and VMIN instructions. This allows us to get the right behaviour for NaN and negative zero. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Correct ABD's handling of negative zeroesPeter Maydell2011-04-031-3/+1
| | | | | | | | | | | Implement ABD by taking the absolute value of the difference of the operands (as the ARM ARM specifies) rather than by flipping the order of the operands to the subtract based on the results of a comparison. The latter approch gives the wrong answers for some edge cases like negative zero. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Fix VCLE.F32 #0, VCLT.F32 #0 NaN handlingPeter Maydell2011-04-031-6/+12
| | | | | | | | | | Implementing the floating-point versions of VCLE #0 and VCLT #0 by doing a GT comparison and inverting the result gives the wrong result if the input is a NaN. Implement as a GT comparison with the operands swapped instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Return right result for Neon comparison with NaNsPeter Maydell2011-04-031-10/+18
| | | | | | | | | Fix the helper functions implementing the Neon floating point comparison ops (VCGE, VCGT, VCEQ, VACGT, VACGE) to return the right answer when one of the values being compared is a NaN. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm/neon_helper.c: Use make_float32/float32_val macrosPeter Maydell2011-04-031-39/+17
| | | | | | | | | | Use the softfloat make_float32 and float32_val macros to convert between softfloat's float32 type and raw uint32_t types, rather than private conversion functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Don't leak TCG temp for UNDEFs in Neon load/store spacePeter Maydell2011-04-011-2/+6
| | | | | | | | | | Move the allocation and freeing of the TCG temp used for the address for Neon load/store instructions so that we don't allocate the temporary until we've done enough decoding to know that the instruction is not an UNDEF pattern; this avoids leaking the TCG temp in these cases. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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