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* target-arm: make PAR bankedFabian Aggeler2014-12-112-11/+22
* target-arm: make IFAR/DFAR bankedFabian Aggeler2014-12-113-9/+28
* target-arm: make DFSR bankedFabian Aggeler2014-12-112-4/+13
* target-arm: make IFSR bankedFabian Aggeler2014-12-112-5/+18
* target-arm: make DACR bankedFabian Aggeler2014-12-112-12/+29
* target-arm: make TTBCR bankedFabian Aggeler2014-12-113-31/+58
* target-arm: make TTBR0/1 bankedFabian Aggeler2014-12-112-14/+43
* target-arm: make CSSELR bankedFabian Aggeler2014-12-112-4/+20
* target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFIFabian Aggeler2014-12-111-0/+54
* target-arm: add SCTLR_EL3 and make SCTLR bankedFabian Aggeler2014-12-114-34/+58
* target-arm: add MVBAR supportFabian Aggeler2014-12-112-6/+10
* target-arm: add SDER definitionGreg Bellows2014-12-112-0/+9
* target-arm: add NSACR registerFabian Aggeler2014-12-112-0/+5
* target-arm: implement IRQ/FIQ routing to Monitor modeFabian Aggeler2014-12-111-0/+9
* target-arm: move AArch32 SCR into security reglistFabian Aggeler2014-12-111-6/+13
* target-arm: insert AArch32 cpregs twice into hashtableFabian Aggeler2014-12-111-17/+81
* target-arm: add secure state bit to CPREG hashPeter Maydell2014-12-114-16/+36
* target-arm: add CPREG secure state supportFabian Aggeler2014-12-111-2/+34
* target-arm: add non-secure Translation Block flagSergey Fedorov2014-12-113-0/+29
* target-arm: add banked register accessorsFabian Aggeler2014-12-111-0/+27
* target-arm: add async excp target_el functionGreg Bellows2014-12-111-19/+97
* target-arm: extend async excp maskingGreg Bellows2014-12-111-14/+52
* Pass semihosting exit code back to system.Liviu Ionescu2014-12-111-2/+9
* target-arm: handle address translations that start at level 3Peter Maydell2014-11-171-9/+11
* target-arm: Correct condition for taking VIRQ and VFIQPeter Maydell2014-11-041-2/+2
* target-arm: Separate out M profile cpu_exec_interrupt handlingPeter Maydell2014-11-042-24/+41
* target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn()Peter Maydell2014-11-041-6/+5
* target-arm/translate.c: Don't pass CPUARMState around in the decoderPeter Maydell2014-11-041-44/+50
* target-arm/translate.c: Don't use IS_M()Peter Maydell2014-11-041-8/+11
* target-arm/translate.c: Use arm_dc_feature() rather than arm_feature()Peter Maydell2014-11-041-60/+80
* target-arm/translate.c: Use arm_dc_feature() in ENABLE_ARCH_ macrosPeter Maydell2014-11-041-8/+8
* target-arm: A64: remove redundant storeAlex Bennée2014-11-021-1/+0
* target-arm: A32: Emulate the SMC instructionFabian Aggeler2014-10-242-2/+12
* target-arm: make arm_current_el() return EL3Fabian Aggeler2014-10-241-9/+20
* target-arm: rename arm_current_pl to arm_current_elGreg Bellows2014-10-248-47/+50
* target-arm: reject switching to monitor modeSergey Fedorov2014-10-241-0/+2
* target-arm: add arm_is_secure() functionFabian Aggeler2014-10-241-0/+47
* target-arm: increase arrays of registers R13 & R14Fabian Aggeler2014-10-242-4/+4
* target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0Peter Maydell2014-10-241-0/+3
* target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any"Peter Maydell2014-10-241-1/+1
* target-arm: Correct sense of the DCZID DZP bitPeter Maydell2014-10-242-3/+3
* target-arm: add emulation of PSCI calls for system emulationRob Herring2014-10-249-3/+301
* target-arm: Add support for A32 and T32 HVC and SMC insnsPeter Maydell2014-10-243-11/+104
* target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpersPeter Maydell2014-10-242-9/+12
* target-arm: add missing PSCI constants needed for PSCI emulationArd Biesheuvel2014-10-241-0/+40
* target-arm: do not set do_interrupt handlers for ARM and AArch64 user modesRob Herring2014-10-244-6/+6
* target-arm: add powered off cpu stateRob Herring2014-10-243-3/+12
* gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flagPeter Maydell2014-10-061-0/+1
* target-arm: Add support for VIRQ and VFIQEdgar E. Iglesias2014-09-295-14/+76
* target-arm: Add IRQ and FIQ routing to EL2 and 3Edgar E. Iglesias2014-09-292-0/+27
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