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* Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150212' into stagingPeter Maydell2015-02-132-14/+6
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| * tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-122-12/+6
| * tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson2015-02-122-2/+0
* | target-arm: A64: Avoid signed shifts in disas_ldst_pair()Peter Maydell2015-02-131-1/+1
* | target-arm: A64: Avoid left shifting negative integers in disas_pc_rel_addrPeter Maydell2015-02-131-2/+3
* | target-arm: A64: Fix handling of rotate in logic_imm_decode_wmaskPeter Maydell2015-02-131-1/+4
* | target-arm: A64: Fix shifts into sign bitPeter Maydell2015-02-131-3/+3
* | target-arm: Add AArch32 guest support to KVM64Greg Bellows2015-02-131-3/+33
* | target-arm: Add 32/64-bit register syncGreg Bellows2015-02-134-8/+216
* | target-arm: Add CPU property to disable AArch64Greg Bellows2015-02-132-1/+43
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* target-arm: fix for exponent comparison in recpe_f64Ildar Isaev2015-02-051-1/+1
* target-arm: Guest cpu endianness determination for virtio KVM ARM/ARM64Pranavkumar Sawargaonkar2015-02-052-0/+26
* target-arm: KVM64: Get and Sync up guest register state like kvm32.Pranavkumar Sawargaonkar2015-02-051-1/+12
* target-arm: Fix brace style in reindented codePeter Maydell2015-02-051-13/+23
* target-arm: Reindent ancient page-table-walk codePeter Maydell2015-02-051-96/+96
* target-arm: Use mmu_idx in get_phys_addr()Peter Maydell2015-02-051-51/+163
* target-arm: Pass mmu_idx to get_phys_addr()Peter Maydell2015-02-051-14/+96
* target-arm: Split AArch64 cases out of ats_write()Peter Maydell2015-02-051-7/+26
* target-arm: Don't define any MMU_MODE*_SUFFIXesPeter Maydell2015-02-051-2/+0
* target-arm: Use correct mmu_idx for unprivileged loads and storesPeter Maydell2015-02-052-3/+42
* target-arm: Define correct mmu_idx values and pass them in TB flagsPeter Maydell2015-02-055-29/+102
* target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STTPeter Maydell2015-02-051-1/+1
* target-arm: Make arm_current_el() return sensible values for M profilePeter Maydell2015-02-051-0/+4
* target-arm: check that LSB <= MSB in BFI instructionKirill Batuzov2015-02-051-0/+4
* target-arm: Squash input denormals in FRECPS and FRSQRTSPeter Maydell2015-02-051-0/+12
* Fix FMULX not squashing denormalized inputs when FZ is set.Xiangyu Hu2015-02-051-0/+6
* target-arm: Add checks that cpreg raw accesses are handledPeter Maydell2015-02-051-0/+31
* target-arm: Split NO_MIGRATE into ALIAS and NO_RAWPeter Maydell2015-02-052-108/+117
* target-arm: Add missing SP_ELx register definitionGreg Bellows2015-02-051-0/+8
* target-arm: Change reset to highest available ELGreg Bellows2015-02-051-1/+8
* target-arm: Add extended RVBAR supportGreg Bellows2015-02-051-6/+25
* target-arm: Fix RVBAR_EL1 register encodingGreg Bellows2015-02-051-1/+1
* vmstate: accept QEMUTimer in VMSTATE_TIMER*, add VMSTATE_TIMER_PTR*Paolo Bonzini2015-01-261-2/+2
* exec.c: Drop TARGET_HAS_ICE define and checksPeter Maydell2015-01-201-2/+0
* target-arm: crypto: fix BE host supportArd Biesheuvel2015-01-161-51/+63
* target-arm: Fix typo in comment (seperately -> separately)Stefan Weil2015-01-151-1/+1
* kvm: extend kvm_irqchip_add_msi_route to work on s390Frank Blaschka2015-01-121-0/+6
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2015-01-092-6/+6
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| * gen-icount: check cflags instead of use_icount globalPaolo Bonzini2015-01-032-2/+2
| * translate: check cflags instead of use_icount globalPaolo Bonzini2015-01-032-4/+4
* | target-arm: add cpu feature EL3 to CPUs with Security ExtensionsFabian Aggeler2014-12-221-0/+4
* | target-arm: Add ARMCPU secure propertyGreg Bellows2014-12-222-0/+25
* | target-arm: Add feature unset functionGreg Bellows2014-12-221-0/+5
* | target-arm: Merge EL3 CP15 register listsGreg Bellows2014-12-221-31/+24
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* target-arm: Check error conditions on kvm_arm_reset_vcpuChristoffer Dall2014-12-111-2/+11
* target-arm: Support save/load for 64 bit CPUsPeter Maydell2014-12-111-3/+19
* target-arm/kvm: make reg sync code common between kvm32/64Alex Bennée2014-12-114-101/+137
* target-arm: make MAIR0/1 bankedGreg Bellows2014-12-112-4/+29
* target-arm: make c13 cp regs banked (FCSEIDR, ...)Fabian Aggeler2014-12-113-19/+77
* target-arm: make VBAR bankedGreg Bellows2014-12-112-3/+12
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