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* target-arm: Update PC before calling gen_helper_check_breakpoints()Sergey Fedorov2015-11-122-0/+2
* target-arm: Clean up DISAS_UPDATE usage in AArch32 translation codeSergey Fedorov2015-11-101-11/+14
* target-arm: Fix gdb singlestep handling in arm_debug_excp_handler()Sergey Fedorov2015-11-101-1/+7
* target-arm: Report S/NS status in the CPU debug logsPeter Maydell2015-11-032-2/+21
* target-arm: Bring AArch64 debug CPU display of PSTATE into line with AArch32Peter Maydell2015-11-031-3/+5
* target-arm: Add and use symbolic names for register banksSoren Brinkmann2015-11-034-39/+56
* target-*: Advance pc after recognizing a breakpointRichard Henderson2015-10-282-4/+10
* target-arm: Add support for S1 + S2 MMU translationsEdgar E. Iglesias2015-10-272-7/+32
* target-arm: Route S2 MMU faults to EL2Edgar E. Iglesias2015-10-271-2/+8
* target-arm: Add S2 translation to 32bit S1 PTWsEdgar E. Iglesias2015-10-271-5/+17
* target-arm: Add S2 translation to 64bit S1 PTWsEdgar E. Iglesias2015-10-272-4/+50
* target-arm: Add ARMMMUFaultInfoEdgar E. Iglesias2015-10-273-14/+36
* target-arm: Avoid inline for get_phys_addrEdgar E. Iglesias2015-10-271-8/+8
* target-arm: Add support for S2 page-table protection bitsEdgar E. Iglesias2015-10-271-4/+37
* target-arm: Add computation of starting level for S2 PTWEdgar E. Iglesias2015-10-272-13/+126
* target-arm: lpae: Rename granule_sz to strideEdgar E. Iglesias2015-10-271-15/+15
* target-arm: lpae: Replace tsz with computed inputsizeEdgar E. Iglesias2015-10-271-11/+11
* target-arm: Add support for AArch32 S2 negative t0szEdgar E. Iglesias2015-10-271-1/+17
* target-arm: lpae: Move declaration of t0sz and t1szEdgar E. Iglesias2015-10-271-2/+3
* target-arm: lpae: Make t0sz and t1sz signed integersEdgar E. Iglesias2015-10-271-2/+2
* target-arm: Add HPFAR_EL2Edgar E. Iglesias2015-10-272-0/+13
* target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ)Soren Brinkmann2015-10-271-0/+16
* target-arm/translate.c: Handle non-executable page-straddling Thumb insnsPeter Maydell2015-10-271-1/+44
* target-arm: Fix "no 64-bit EL2" assumption in arm_excp_unmasked()Peter Maydell2015-10-271-30/+52
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2015-10-191-1/+1
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| * kvm: Pass PCI device pointer to MSI routing functionsPavel Fedin2015-10-191-1/+1
* | target-arm: Fix CPU breakpoint handlingSergey Fedorov2015-10-164-21/+46
* | target-arm: Fix GDB breakpoint handlingSergey Fedorov2015-10-161-0/+6
* | target-arm: implement arm_debug_target_el()Sergey Fedorov2015-10-161-1/+16
* | target-arm: Add MDCR_EL2Sergey Fedorov2015-10-162-0/+13
* | target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregsDavorin Mista2015-10-162-2/+24
* | target-arm: Avoid calling arm_el_is_aa64() function for unimplemented ELSergey Sorokin2015-10-162-5/+21
* | target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin2015-10-163-4/+27
* | target-arm: Add missing 'static' attributeStefan Weil2015-10-161-1/+1
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* qdev: Protect device-list-properties against broken devicesMarkus Armbruster2015-10-091-0/+11
* tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-073-78/+14
* tcg: Pass data argument to restore_state_to_opcRichard Henderson2015-10-071-4/+5
* tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-072-1/+8
* target-*: Drop cpu_gen_code defineRichard Henderson2015-10-071-1/+0
* target-arm: Add condexec state to insn_startRichard Henderson2015-10-073-2/+4
* target-*: Introduce and use cpu_breakpoint_testRichard Henderson2015-10-072-28/+29
* target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson2015-10-072-6/+7
* target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson2015-10-072-8/+2
* tcg: Rename debug_insn_start to insn_startRichard Henderson2015-10-072-2/+2
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2015-09-251-2/+0
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| * arm: Remove ELF_MACHINE from cpu.hPeter Crosthwaite2015-09-251-2/+0
* | arm: clarify the use of muldiv64()Laurent Vivier2015-09-251-6/+8
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* hw/intc: Initial implementation of vGICv3Pavel Fedin2015-09-242-0/+28
* arm_kvm: Do not assume particular GIC type in kvm_arch_irqchip_create()Pavel Fedin2015-09-242-7/+21
* target-arm: Use new revbit functionsRichard Henderson2015-09-152-25/+2
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