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target-arm
Commit message (
Expand
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Author
Age
Files
Lines
*
target-arm: Use new revbit functions
Richard Henderson
2015-09-15
2
-25
/
+2
*
target-arm: Add VMPIDR_EL2
Edgar E. Iglesias
2015-09-14
2
-2
/
+25
*
target-arm: Break out mpidr_read_val()
Edgar E. Iglesias
2015-09-14
1
-1
/
+6
*
target-arm: Add VPIDR_EL2
Edgar E. Iglesias
2015-09-14
2
-1
/
+42
*
target-arm: Suppress EPD for S2, EL2 and EL3 translations
Edgar E. Iglesias
2015-09-14
1
-2
/
+4
*
target-arm: Suppress TBI for S2 translations
Edgar E. Iglesias
2015-09-14
1
-1
/
+3
*
target-arm: Add VTTBR_EL2
Edgar E. Iglesias
2015-09-14
2
-2
/
+33
*
target-arm: Add VTCR_EL2
Edgar E. Iglesias
2015-09-14
2
-2
/
+42
*
target-arm: Use tcg_gen_extrh_i64_i32
Richard Henderson
2015-09-14
1
-25
/
+9
*
target-arm: Recognize ROR
Richard Henderson
2015-09-14
1
-12
/
+21
*
target-arm: Eliminate unnecessary zero-extend in disas_bitfield
Richard Henderson
2015-09-14
1
-1
/
+5
*
target-arm: Recognize UXTB, UXTH, LSR, LSL
Richard Henderson
2015-09-14
1
-0
/
+17
*
target-arm: Recognize SXTB, SXTH, SXTW, ASR
Richard Henderson
2015-09-14
1
-1
/
+23
*
target-arm: Implement fcsel with movcond
Richard Henderson
2015-09-14
1
-28
/
+17
*
target-arm: Implement ccmp branchless
Richard Henderson
2015-09-14
1
-16
/
+58
*
target-arm: Use setcond and movcond for csel
Richard Henderson
2015-09-14
1
-36
/
+49
*
target-arm: Handle always condition codes within arm_test_cc
Richard Henderson
2015-09-14
1
-0
/
+9
*
target-arm: Introduce DisasCompare
Richard Henderson
2015-09-14
2
-46
/
+78
*
target-arm: Share all common TCG temporaries
Richard Henderson
2015-09-14
3
-27
/
+13
*
tlb: Add "ifetch" argument to cpu_mmu_index()
Benjamin Herrenschmidt
2015-09-11
2
-4
/
+4
*
typofixes - v4
Veres Lajos
2015-09-11
1
-2
/
+2
*
maint: remove / fix many doubled words
Daniel P. Berrange
2015-09-11
3
-4
/
+4
*
target-arm: Add AArch64 access to PAR_EL1
Edgar E. Iglesias
2015-09-08
1
-0
/
+6
*
target-arm: Correct opc1 for AT_S12Exx
Edgar E. Iglesias
2015-09-08
1
-4
/
+4
*
target-arm: Log the target EL when taking exceptions
Edgar E. Iglesias
2015-09-08
1
-1
/
+2
*
target-arm: Fix default_exception_el() function for the case when EL3 is not ...
Sergey Sorokin
2015-09-08
3
-4
/
+13
*
target-arm: Refactor CPU affinity handling
Pavel Fedin
2015-09-07
4
-5
/
+16
*
target-arm: Fix arm_excp_unmasked() function
Sergey Sorokin
2015-09-07
1
-3
/
+3
*
target-arm: Fix AArch32:AArch64 general-purpose register mapping
Sergey Sorokin
2015-09-07
1
-32
/
+32
*
arm: Remove hw_error() usages.
Peter Crosthwaite
2015-09-07
2
-3
/
+3
*
arm: cpu: assert() on no-EL2 virt IRQ error condition.
Peter Crosthwaite
2015-09-07
1
-4
/
+1
*
target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
Peter Maydell
2015-09-07
4
-2
/
+31
*
target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block
Peter Maydell
2015-09-07
1
-3
/
+18
*
target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call
Peter Maydell
2015-09-07
1
-0
/
+10
*
target-arm/arm-semi.c: Support widening APIs to 64 bits
Peter Maydell
2015-09-07
2
-13
/
+58
*
target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]'
Peter Maydell
2015-09-07
1
-32
/
+47
*
target-arm: Improve semihosting debug prints
Christopher Covington
2015-09-07
1
-3
/
+9
*
target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb
Peter Maydell
2015-09-07
1
-1
/
+1
*
target-arm: Implement AArch64 TLBI operations on IPAs
Peter Maydell
2015-08-25
1
-0
/
+55
*
target-arm: Implement missing EL3 TLB invalidate operations
Peter Maydell
2015-08-25
1
-0
/
+76
*
target-arm: Implement missing EL2 TLBI operations
Peter Maydell
2015-08-25
1
-0
/
+22
*
target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch
Peter Maydell
2015-08-25
1
-43
/
+129
*
target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order
Peter Maydell
2015-08-25
1
-8
/
+8
*
target-arm: Implement AArch32 ATS1H* operations
Peter Maydell
2015-08-25
1
-0
/
+22
*
target-arm: Enable the AArch32 ATS12NSO ops
Peter Maydell
2015-08-25
1
-5
/
+11
*
target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3
Peter Maydell
2015-08-25
2
-0
/
+11
*
target-arm: Wire up AArch64 EL2 and EL3 address translation ops
Peter Maydell
2015-08-25
1
-2
/
+41
*
target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations
Peter Maydell
2015-08-25
1
-0
/
+5
*
target-arm: Implement missing ACTLR registers
Peter Maydell
2015-08-25
1
-6
/
+15
*
target-arm: Implement missing AFSR registers
Peter Maydell
2015-08-25
1
-0
/
+24
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