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* target-arm: Drop cpu_arm_close()Andreas Färber2012-03-292-6/+0
| | | | | | | It's unused, so no need to QOM'ify it later. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Decode SETEND correctly in ThumbPeter Maydell2012-03-151-23/+40
| | | | | | | | | | | | | | Decode the SETEND instruction correctly in Thumb mode, rather than accidentally treating it like CPS. We don't support BE8 mode, but this change brings the Thumb mode in to line with behaviour in ARM mode: 'SETEND BE' is not supported and will provoke an UNDEF exception, but 'SETEND LE' is correctly handled as a no-op. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reported-by: Daniel Forsgren <daniel.forsgren@enea.com> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
* target-arm: Clear IT bits when taking exceptions in v7MPeter Maydell2012-03-151-1/+2
| | | | | | | | | When taking an exception for an M profile core, we must clear the IT bits. Since the IT bits are cached in env->condexec_bits we must clear them there: writing the bits in env->uncached_cpsr has no effect. (Reported as LP:944645.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Fix typo in ARM946 cp15 c5 handlingPeter Maydell2012-03-151-1/+1
| | | | | | | | Fix a typo in handling of the ARM946 cp15 c5 c0 0 1 handling (instruction access permission bits) that meant it would return the data access permission bits by mistake. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Rename CPUState -> CPUArchStateAndreas Färber2012-03-141-1/+1
| | | | | | | | | | | | | Scripted conversion: for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done All occurrences of CPUArchState are expected to be replaced by QOM CPUState, once all targets are QOM'ified and common fields have been extracted. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
* target-arm: Don't overuse CPUStateAndreas Färber2012-03-146-195/+195
| | | | | | | | | | Scripted conversion: sed -i "s/CPUState/CPUARMState/g" target-arm/*.[hc] sed -i "s/#define CPUARMState/#define CPUState/" target-arm/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com> Acked-by: Peter Maydell <peter.maydell@linaro.org>
* Rename cpu_reset() to cpu_state_reset()Andreas Färber2012-03-141-2/+2
| | | | | | | | | | Frees the identifier cpu_reset for QOM CPUs (manual rename). Don't hide the parameter type behind explicit casts, use static functions with strongly typed argument to indirect. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
* target-arm: Clean includesStefan Weil2012-02-281-5/+0
| | | | | | | Remove some include statements which are not needed. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <sw@weilnetz.de>
* target-arm/helper.c: tb_flush() on CPU resetPeter Maydell2012-02-171-0/+5
| | | | | | | | | | Since target-arm has some CPUState fields for which we take the approach of baking assumptions about them into translated code and then calling tb_flush() when the fields change, we must also tb_flush on CPU reset, because reset is a change of those fields. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* target-arm/helper.c: Correct FPSID value for Cortex-A9Peter Maydell2012-02-171-1/+1
| | | | | | | | The correct FPSID for the Cortex-A9 (according to the TRM) is 0x41033090 for the r0p0 that we claim to model. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* Add Cortex-A15 CPU definitionPeter Maydell2012-01-252-5/+52
| | | | | | | | | | | | | | | Add a definition of a Cortex-A15 CPU. Note that for the moment we do not implement any of: * Large Physical Address Extensions (LPAE) * Virtualization Extensions * Generic Timer * TrustZone (this is also true of our existing Cortex-A9 model, etc) This CPU model is sufficient to boot a Linux kernel which has been compiled for an A15 without LPAE enabled. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Add dummy implementation of generic timer cp15 registersPeter Maydell2012-01-252-2/+11
| | | | | | | | | | Add a dummy implementation of the cp15 registers for the generic timer (found in the Cortex-A15), just sufficient for Linux to decide that it can't use it. This requires at least CNTP_CTL and CNTFRQ to be implemented as RAZ/WI; we RAZ/WI all of c14. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: store the config_base_register during cpu_resetMark Langsdorf2012-01-251-0/+3
| | | | | | | | | Long term, the config_base_register will be a QDM parameter. In the meantime, models that use it need to be able to preserve it across cpu_reset() calls. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm/helper.c: Don't assume softfloat int32 is 32 bits onlyPeter Maydell2012-01-251-1/+1
| | | | | | | | | | | | In the helper routines for VCVT float-to-int conversions, add an explicit cast rather than relying on the softfloat int32 type being exactly 32 bits wide (which it is not guaranteed to be). Without this, if the softfloat type was 64 bits wide we would get zero-extension of the 32 bit value from the ARM register rather than sign-extension, since TCG i32 values are passed as uint32_t. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Fix implementation of TLB invalidate operationsPeter Maydell2012-01-251-7/+6
| | | | | | | | | | | | | | | Fix some bugs in the implementation of the TLB invalidate operations on ARM: * the 'invalidate all' op was not passing flush_global=1 to tlb_flush(); this doesn't have a practical effect since tlb_flush() currently ignores that argument, but is semantically incorrect * 'invalidate by address for all ASIDs' was implemented as flushing the whole TLB, which invalidates much more than strictly necessary. Use tlb_flush_page() instead. We also annotate the ops with the ARM ARM official acronyms. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: Add dummy support for co-processor 15's secure config registerRob Herring2012-01-133-1/+13
| | | | | | Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Fix errors in decode of M profile CPSPeter Maydell2012-01-131-4/+4
| | | | | | | | | | | Fix errors in the decode of M profile CPS: * the decode of the I (affects PRIMASK) and F (affects FAULTMASK) bits was reversed * the FAULTMASK system register number is 19, not 17 This fixes an issue reported as LP:913925. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: add dummy A9-specific cp15 registersMark Langsdorf2012-01-053-1/+59
| | | | | | | | | | | Add dummy register support for the cp15, CRn=c15 registers. config_base_register and power_control_register currently default to 0, but may have improved support after the QOM CPU patches are finished. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Ignore attempts to set invalid modes in CPSRPeter Maydell2012-01-051-1/+29
| | | | | | | | | Ignore attempts to set the CPSR mode field to an invalid value. This is UNPREDICTABLE, but we should not cpu_abort() for things a malicious guest (or a confused user on the gdbstub interface) can provoke. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Don't use cpu_single_env in bank_number()Peter Maydell2012-01-051-6/+6
| | | | | | | | Avoid using cpu_single_env in bank_number() -- if we were called via the gdb stub reading or writing the CPSR then it is NULL and we will segfault if we take the cpu_abort(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Infer VFPv3 feature from VFPv4Andreas Färber2011-12-131-1/+3
| | | | | | | VFP4 => VFP3 Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Infer VFP feature from VFPv3Andreas Färber2011-12-131-3/+3
| | | | | | | VFP3 => VFP Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Infer Thumb division feature from M profileAndreas Färber2011-12-131-1/+3
| | | | | | | M => THUMB_DIV Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Infer Thumb2 feature from ARMv7Andreas Färber2011-12-131-4/+1
| | | | | | | V7 => THUMB2 Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Infer AUXCR feature from ARMv6Andreas Färber2011-12-131-5/+3
| | | | | | | V6 && !M => AUXCR Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Infer ARMv6(K) feature from ARMv7Andreas Färber2011-12-131-4/+5
| | | | | | | | V7 && M => V6 V7 && !M => V6K Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Infer ARMv6 feature from v6KAndreas Färber2011-12-131-5/+3
| | | | | | | V6K => V6 Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Infer ARMv5 feature from ARMv6Andreas Färber2011-12-131-7/+3
| | | | | | | V6 => V5 Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Infer ARMv4T feature from ARMv5Andreas Färber2011-12-131-12/+3
| | | | | | | V5 => V4T Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: Fix CP15 FSR (C5) domain settingJean-Christophe DUBOIS2011-12-131-11/+15
| | | | | | | | | Return the correct value in the domain field in the cp15 DFSR (C5) -- bug noticed during Xvisor development. Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net> [Peter Maydell: reworded commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm/helper.c: Don't allocate TCG resources unless TCG enabledPeter Maydell2011-12-051-1/+1
| | | | | | | | Don't call arm_translate_init() (which allocates TCG resources) unless TCG is enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* target-arm/translate.c: Fix slightly misleading comment in Thumb decoderPeter Maydell2011-12-051-3/+5
| | | | | | | | | | Clarify some slightly misleading comments in the Thumb decoder's handling of the memory hint space -- in particular one code path marked as 'UNPREDICTABLE or unallocated hint' also includes some legitimate preload instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* target-arm: Fix use of free() in cpu_arm_close()Andreas Färber2011-10-201-1/+1
| | | | | | | env is allocated in cpu_arm_init() with g_malloc0(), so free with g_free(). Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm/machine.c: Restore VFP registers correctlyDmitry Koshelev2011-10-191-1/+1
| | | | | | | | | Fix the restoring of VFP registers on vmload. Signed-off-by: Dmitry Koshelev <karaghiozis@gmail.com> Reviewed-by: Juan Quintela <quintela@redhat.com> [peter.maydell: improved commit message a little] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement VFPv4 fused multiply-accumulate insnsPeter Maydell2011-10-194-0/+90
| | | | | | | Implement the fused multiply-accumulate instructions (VFMA, VFMS, VFNMA, VFNMS) which are new in VFPv4. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add ARM UDIV/SDIV supportPeter Maydell2011-10-193-1/+24
| | | | | | | | Add support for UDIV and SDIV in ARM mode. This is a new optional feature for A profile cores (Thumb mode has had UDIV and SDIV for M profile cores for some time). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIVPeter Maydell2011-10-193-4/+5
| | | | | | | | | | Rename the ARM_FEATURE_DIV feature bit to _THUMB_DIV, to make room for a new feature switch enabling DIV in the ARM encoding. (Cores may implement either (a) no divide insns (b) divide insns in Thumb encodings only (c) divide insns in both ARM and Thumb encodings.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: v6 media multiply space: UNDEF on unassigned encodingsPeter Maydell2011-10-191-4/+20
| | | | | | | | Clean up the decoding of the v6 media multiply space so that we UNDEF on unassigned encodings rather than randomly interpreting them as some instruction in this space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* rsqrte_f32: No need to copy sign bit.Christophe LYON2011-10-191-2/+1
| | | | | | | Indeed, the result is known to be always positive. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge remote-tracking branch 'stefanha/trivial-patches' into stagingAnthony Liguori2011-10-101-1/+1
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| * target-arm: Fix typoAndreas Färber2011-10-051-1/+1
| | | | | | | | | | | | | | | | | | The command line option is called -kernel, not -kenrel. Cc: Paul Brook <paul@codesourcery.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* | ARM: fix segfaultBlue Swirl2011-10-081-0/+1
|/ | | | | | | | | Fix a bug in bccd9ec5f098668576342c83d90d6d6833d61d33, target-arm/op_helper.c missed a change unlike all other targets. This lead to a NULL pointer dereferences. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* softmmu_header: pass CPUState to tlb_fillBlue Swirl2011-10-011-4/+2
| | | | | | | Pass CPUState pointer to tlb_fill() instead of architecture local cpu_single_env hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Use glib memory allocation and free functionsAnthony Liguori2011-08-201-1/+1
| | | | | | qemu_malloc/qemu_free no longer exist after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Merge remote-tracking branch 'pm-arm/for-upstream' into pmEdgar E. Iglesias2011-08-093-42/+121
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| * target-arm: Don't print debug messages for various UNDEF casesPeter Maydell2011-07-261-6/+0
| | | | | | | | | | | | | | | | Remove some stray printfs for cases which don't generally happen (some VFP UNDEF cases, reads and writes to unknown cp14 registers); we should simply generate an UNDEF when the instruction is executed. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: UNDEF on a VCVTT/VCVTB UNPREDICTABLE to avoid TCG assertPeter Maydell2011-07-261-8/+11
| | | | | | | | | | | | | | | | | | | | | | VCVTT/VCVTB with bit 8 set is UNPREDICTABLE; we choose to UNDEF. This avoids a TCG assert later when the VCVTT/VCVTB code tries to use a source register that wasn't ever set up. We pull the check for the presence of the half-precision extension up in to this common code as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: Handle UNDEF and UNPREDICTABLE cases for VLDM, VSTMPeter Maydell2011-07-261-7/+31
| | | | | | | | | | | | | | | | Handle the UNDEF and UNPREDICTABLE cases for VLDM and VSTM. In particular, we now generate an undef exception for overlarge imm8 values rather than generating 1000+ TCG ops and hitting an assertion. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: Support v6 barriers in linux-user modePeter Maydell2011-07-261-18/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv6 implemented various operations as special cases of cp15 accesses which are true instructions in v7; this includes barriers (DMB, DSB, ISB). Catch this special case at translate time, so that it works in linux-user mode (which doesn't provide a functional get_cp15 helper) as well as system mode. Includes minor cleanup of the existing cases (single switch statement, and doing the "OK in user mode?" test explicitly rather than hiding it in cp15_user_ok()). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm: Mark 1136r1 as a v6K corePeter Maydell2011-07-262-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | The 1136r1 is actually a v6K core (unlike the 1136r0); mark it as such, thus enabling the TLS registers, NOP hints, CLREX, half and byte wide exclusive load/stores, etc. The VA-to-PA translation registers are not present on 1136r1, so introduce a new feature flag for them, which is enabled on 1176, 11MPCore and all v7 cores. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jamie Iles <jamie@jamieiles.com>
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