| Commit message (Expand) | Author | Age | Files | Lines |
* | target-arm: Add support for long format translation table walks | Peter Maydell | 2012-07-12 | 1 | -0/+182 |
* | target-arm: Implement TTBCR changes for LPAE | Peter Maydell | 2012-07-12 | 1 | -1/+14 |
* | target-arm: Implement long-descriptor PAR format | Peter Maydell | 2012-07-12 | 1 | -10/+69 |
* | target-arm: Use target_phys_addr_t in get_phys_addr() | Peter Maydell | 2012-07-12 | 1 | -14/+15 |
* | target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE | Peter Maydell | 2012-07-12 | 3 | -3/+87 |
* | target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE | Peter Maydell | 2012-07-12 | 1 | -0/+5 |
* | target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers | Peter Maydell | 2012-07-12 | 1 | -0/+16 |
* | target-arm: Extend feature flags to 64 bits | Peter Maydell | 2012-07-12 | 3 | -6/+6 |
* | target-arm: Implement privileged-execute-never (PXN) | Peter Maydell | 2012-07-12 | 3 | -12/+26 |
* | ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits | Peter Maydell | 2012-07-12 | 1 | -1/+1 |
* | target-arm: Fix TCG temp handling in 64 bit cp writes | Peter Maydell | 2012-07-12 | 1 | -0/+2 |
* | target-arm: Fix some copy-and-paste errors in cp register names | Peter Maydell | 2012-07-12 | 1 | -3/+3 |
* | target-arm: Fix typo that meant TTBR1 accesses went to TTBR0 | Peter Maydell | 2012-07-12 | 1 | -1/+1 |
* | target-arm: Fix CP15 based WFI | Paul Brook | 2012-07-12 | 1 | -1/+1 |
* | target-arm: Remove ARM_CPUID_* macros | Peter Maydell | 2012-06-20 | 2 | -52/+25 |
* | target-arm: Remove remaining old cp15 infrastructure | Peter Maydell | 2012-06-20 | 3 | -100/+1 |
* | target-arm: Move block cache ops to new cp15 framework | Peter Maydell | 2012-06-20 | 2 | -6/+14 |
* | target-arm: Remove c0_cachetype CPUARMState field | Peter Maydell | 2012-06-20 | 2 | -4/+1 |
* | target-arm: Convert final ID registers | Peter Maydell | 2012-06-20 | 2 | -50/+68 |
* | target-arm: Convert MPIDR | Peter Maydell | 2012-06-20 | 3 | -22/+31 |
* | target-arm: Convert cp15 cache ID registers | Peter Maydell | 2012-06-20 | 3 | -32/+33 |
* | target-arm: Convert cp15 crn=0 crm={1,2} feature registers | Peter Maydell | 2012-06-20 | 3 | -24/+54 |
* | target-arm: Convert cp15 crn=1 registers | Peter Maydell | 2012-06-20 | 3 | -76/+61 |
* | target-arm: Convert cp15 crn=9 registers | Peter Maydell | 2012-06-20 | 2 | -79/+59 |
* | target-arm: Convert cp15 crn=6 registers | Peter Maydell | 2012-06-20 | 2 | -53/+45 |
* | target-arm: convert cp15 crn=7 registers | Peter Maydell | 2012-06-20 | 3 | -11/+74 |
* | target-arm: Convert cp15 VA-PA translation registers | Peter Maydell | 2012-06-20 | 1 | -43/+65 |
* | target-arm: Convert cp15 MMU TLB control | Peter Maydell | 2012-06-20 | 1 | -20/+43 |
* | target-arm: Convert cp15 crn=15 registers | Peter Maydell | 2012-06-20 | 3 | -117/+126 |
* | target-arm: Convert cp15 crn=10 registers | Peter Maydell | 2012-06-20 | 1 | -6/+5 |
* | target-arm: Convert cp15 crn=13 registers | Peter Maydell | 2012-06-20 | 1 | -30/+31 |
* | target-arm: Convert cp15 crn=2 registers | Peter Maydell | 2012-06-20 | 2 | -56/+33 |
* | target-arm: Convert MMU fault status cp15 registers | Peter Maydell | 2012-06-20 | 1 | -81/+107 |
* | target-arm: Convert cp15 c3 register | Peter Maydell | 2012-06-20 | 1 | -6/+12 |
* | target-arm: Convert generic timer cp15 regs | Peter Maydell | 2012-06-20 | 1 | -12/+11 |
* | target-arm: Convert performance monitor registers | Peter Maydell | 2012-06-20 | 3 | -149/+158 |
* | target-arm: Convert TLS registers | Peter Maydell | 2012-06-20 | 2 | -58/+19 |
* | target-arm: Convert WFI/barriers special cases to cp_reginfo | Peter Maydell | 2012-06-20 | 2 | -51/+42 |
* | target-arm: Convert TEECR, TEEHBR to new scheme | Peter Maydell | 2012-06-20 | 3 | -77/+45 |
* | target-arm: Convert debug registers to cp_reginfo | Peter Maydell | 2012-06-20 | 2 | -28/+25 |
* | target-arm: Add register_cp_regs_for_features() | Peter Maydell | 2012-06-20 | 3 | -0/+14 |
* | target-arm: Remove old cpu_arm_set_cp_io infrastructure | Peter Maydell | 2012-06-20 | 4 | -107/+1 |
* | target-arm: initial coprocessor register framework | Peter Maydell | 2012-06-20 | 7 | -3/+546 |
* | target-arm: Fix 11MPCore cache type register value | Peter Maydell | 2012-06-20 | 1 | -1/+1 |
* | build: move other target-*/ objects to nested Makefile.objs | Paolo Bonzini | 2012-06-07 | 1 | -1/+2 |
* | build: move libobj-y variable to nested Makefile.objs | Paolo Bonzini | 2012-06-07 | 1 | -0/+4 |
* | build: move obj-TARGET-y variables to nested Makefile.objs | Paolo Bonzini | 2012-06-07 | 2 | -0/+510 |
* | Kill off cpu_state_reset() | Andreas Färber | 2012-06-04 | 1 | -5/+0 |
* | target-arm: Use cpu_reset() in cpu_arm_init() | Andreas Färber | 2012-06-04 | 1 | -1/+1 |
* | target-arm/cpu.h: Make cpu_init("nonexistent cpu") return NULL | Peter Maydell | 2012-05-10 | 1 | -1/+9 |