hqemu - HQEMU

	Commit message (Expand)	Author	Age	Files	Lines
*	target-arm: A64: Implement unprivileged load/store	Peter Maydell	2014-02-20	1	-32/+37
*	target-arm: A64: Implement narrowing three-reg-diff operations	Peter Maydell	2014-02-20	1	-1/+59
*	target-arm: A64: Implement the wide 3-reg-different operations	Peter Maydell	2014-02-20	1	-1/+40
*	target-arm: A64: Add most remaining three-reg-diff widening ops	Peter Maydell	2014-02-20	1	-21/+88
*	target-arm: A64: Add opcode comments to disas_simd_three_reg_diff	Peter Maydell	2014-02-20	1	-11/+11
*	target-arm: A64: Implement store-exclusive for system mode	Peter Maydell	2014-02-20	1	-6/+62
*	target-arm: Fix incorrect type for value argument to write_raw_cp_reg	Peter Maydell	2014-02-20	1	-1/+1
*	target-arm: Remove failure status return from read/write_raw_cp_reg	Peter Maydell	2014-02-20	1	-24/+12
*	target-arm: Remove unnecessary code now read/write fns can't fail	Peter Maydell	2014-02-20	2	-6/+0
*	target-arm: Drop success/fail return from cpreg read and write functions	Peter Maydell	2014-02-20	4	-208/+137
*	target-arm: Convert miscellaneous reginfo structs to accessfn	Peter Maydell	2014-02-20	1	-25/+19
*	target-arm: Convert generic timer reginfo to accessfn	Peter Maydell	2014-02-20	1	-56/+66
*	target-arm: Convert performance monitor reginfo to accessfn	Peter Maydell	2014-02-20	1	-42/+28
*	target-arm: Split cpreg access checks out from read/write functions	Peter Maydell	2014-02-20	5	-4/+66
*	target-arm: Stop underdecoding ARM946 PRBS registers	Peter Maydell	2014-02-20	1	-23/+24
*	target-arm: Log bad system register accesses with LOG_UNIMP	Peter Maydell	2014-02-20	2	-1/+19
*	target-arm: Remove unused ARMCPUState sr substruct	Peter Maydell	2014-02-20	1	-5/+0
*	target-arm: Restrict check_ap() use of S and R bits to v6 and earlier	Peter Maydell	2014-02-20	1	-0/+3
*	target-arm: Define names for SCTLR bits	Peter Maydell	2014-02-20	3	-9/+61
*	target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs	Peter Maydell	2014-02-20	1	-1/+15
*	target-arm: A64: Implement remaining 3-same instructions	Peter Maydell	2014-02-20	5	-4/+130
*	target-arm: A64: Implement floating point pairwise insns	Alex Bennée	2014-02-20	1	-38/+86
*	target-arm: A64: Implement SIMD FP compare and set insns	Alex Bennée	2014-02-20	3	-12/+207
*	target-arm: A64: Implement scalar three different instructions	Peter Maydell	2014-02-20	1	-1/+94
*	target-arm: A64: Implement SIMD scalar indexed instructions	Peter Maydell	2014-02-20	1	-33/+82
*	target-arm: A64: Implement long vector x indexed insns	Peter Maydell	2014-02-20	1	-5/+139
*	target-arm: A64: Implement plain vector SIMD indexed element insns	Peter Maydell	2014-02-20	3	-1/+275
*	exec: Make stl_*_phys input an AddressSpace	Edgar E. Iglesias	2014-02-11	1	-1/+2
*	exec: Make ldq/ldub_*_phys input an AddressSpace	Edgar E. Iglesias	2014-02-11	1	-1/+2
*	exec: Make ldl_*_phys input an AddressSpace	Edgar E. Iglesias	2014-02-11	1	-6/+9
*	disas: Implement disassembly output for A64	Claudio Fontana	2014-02-08	1	-1/+1
*	target-arm: Add support for AArch32 64bit VCVTB and VCVTT	Will Newton	2014-02-08	1	-22/+61
*	target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group	Peter Maydell	2014-02-08	1	-3/+20
*	target-arm: A64: Add 2-reg-misc REV* instructions	Alex Bennée	2014-02-08	1	-1/+70
*	target-arm: A64: Add narrowing 2-reg-misc instructions	Peter Maydell	2014-02-08	1	-2/+83
*	target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT	Peter Maydell	2014-02-08	3	-6/+41
*	target-arm: A64: Implement 2-register misc compares, ABS, NEG	Peter Maydell	2014-02-08	1	-2/+134
*	target-arm: A64: Add skeleton decode for SIMD 2-reg misc group	Peter Maydell	2014-02-08	1	-1/+109
*	target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc	Peter Maydell	2014-02-08	1	-1/+86
*	target-arm: A64: Implement remaining integer scalar-3-same insns	Peter Maydell	2014-02-08	1	-19/+87
*	target-arm: A64: Implement scalar pairwise ops	Peter Maydell	2014-02-08	1	-1/+113
*	target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD	Peter Maydell	2014-02-08	1	-1/+123
*	target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns	Peter Maydell	2014-02-08	1	-4/+127
*	target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns	Peter Maydell	2014-02-08	1	-22/+112
*	target-arm: A64: Add SIMD shift by immediate	Alex Bennée	2014-01-31	1	-2/+373
*	target-arm: A64: Add simple SIMD 3-same floating point ops	Peter Maydell	2014-01-31	1	-2/+188
*	target-arm: A64: Add integer ops from SIMD 3-same group	Peter Maydell	2014-01-31	1	-1/+164
*	target-arm: A64: Add logic ops from SIMD 3 same group	Peter Maydell	2014-01-31	1	-1/+72
*	target-arm: A64: Add top level decode for SIMD 3-same group	Peter Maydell	2014-01-31	1	-1/+44
*	target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops	Peter Maydell	2014-01-31	1	-1/+130