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* gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flagPeter Maydell2014-10-061-0/+1
* target-arm: Add support for VIRQ and VFIQEdgar E. Iglesias2014-09-295-14/+76
* target-arm: Add IRQ and FIQ routing to EL2 and 3Edgar E. Iglesias2014-09-292-0/+27
* target-arm: A64: Emulate the SMC insnEdgar E. Iglesias2014-09-297-0/+51
* target-arm: Add a Hypervisor Trap exception typeEdgar E. Iglesias2014-09-294-0/+4
* target-arm: A64: Emulate the HVC insnEdgar E. Iglesias2014-09-297-10/+81
* target-arm: A64: Correct updates to FAR and ESR on exceptionsEdgar E. Iglesias2014-09-291-4/+3
* target-arm: Don't take interrupts targeting lower ELsEdgar E. Iglesias2014-09-291-0/+7
* target-arm: Break out exception masking to a separate funcEdgar E. Iglesias2014-09-292-5/+17
* target-arm: A64: Refactor aarch64_cpu_do_interruptEdgar E. Iglesias2014-09-293-11/+33
* target-arm: Add SCR_EL3Edgar E. Iglesias2014-09-292-3/+51
* target-arm: Add HCR_EL2Edgar E. Iglesias2014-09-292-0/+70
* target-arm: Don't handle c15_cpar changes via tb_flush()Peter Maydell2014-09-296-30/+44
* target-arm: Implement handling of breakpoint firingPeter Maydell2014-09-292-15/+66
* target-arm: Implement setting guest breakpointsPeter Maydell2014-09-295-2/+136
* target-arm: Use cpu_exec_interrupt qom hookRichard Henderson2014-09-253-0/+36
* target-arm: Make *IS TLB maintenance ops affect all CPUsPeter Maydell2014-09-121-12/+89
* target-arm: Push legacy wildcard TLB ops back into v6Peter Maydell2014-09-121-47/+55
* target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0Peter Maydell2014-09-121-0/+19
* target-arm: Remove comment about MDSCR_EL1 being dummy implementationPeter Maydell2014-09-121-3/+1
* target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32Peter Maydell2014-09-121-0/+26
* target-arm: Implement handling of fired watchpointsPeter Maydell2014-09-124-1/+204
* target-arm: Move extended_addresses_enabled() to internals.hPeter Maydell2014-09-122-11/+11
* target-arm: Implement setting of watchpointsPeter Maydell2014-09-125-3/+149
* target-arm: Fix broken indentation in arm_cpu_reest()Martin Galvan2014-09-121-1/+1
* target-arm: Fix resetting issues on ARMv7-M CPUsMartin Galvan2014-09-121-10/+22
* target-arm: Implement pmccfiltr_write functionAlistair Francis2014-08-291-0/+9
* target-arm: Remove old code and replace with new functionsAlistair Francis2014-08-291-23/+4
* target-arm: Implement pmccntr_sync functionAlistair Francis2014-08-292-0/+34
* target-arm: Add arm_ccnt_enabled functionAlistair Francis2014-08-291-0/+12
* target-arm: Implement PMCCNTR_EL0 and related registersAlistair Francis2014-08-292-8/+42
* arm: Implement PMCCNTR 32b read-modify-writePeter Crosthwaite2014-08-291-1/+10
* target-arm: Make the ARM PMCCNTR register 64-bitAlistair Francis2014-08-292-11/+10
* target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register valuesPeter Maydell2014-08-291-1/+2
* target-arm: Fix regression that disabled VFP for ARMv5 CPUsPeter Maydell2014-08-291-1/+8
* arm: cortex-a9: Fix cache-line size and associativityPeter Crosthwaite2014-08-191-2/+2
* arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2Christoffer Dall2014-08-191-0/+27
* target-arm: Rename QEMU PSCI v0.1 definitionsChristoffer Dall2014-08-191-11/+11
* target-arm: Implement MDSCR_EL1 as having statePeter Maydell2014-08-191-1/+3
* target-arm: Implement ARMv8 single-stepping for AArch32 codePeter Maydell2014-08-192-2/+95
* target-arm: Implement ARMv8 single-step handling for A64 codePeter Maydell2014-08-196-5/+131
* target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tbPeter Maydell2014-08-191-2/+3
* target-arm: Set PSTATE.SS correctly on exception return from AArch64Peter Maydell2014-08-192-0/+81
* target-arm: Correctly handle PSTATE.SS when taking exception to AArch32Peter Maydell2014-08-191-0/+4
* target-arm: Don't allow AArch32 to access RES0 CPSR bitsPeter Maydell2014-08-193-9/+18
* target-arm: Adjust debug ID registers per-CPUPeter Maydell2014-08-194-7/+31
* target-arm: Provide both 32 and 64 bit versions of debug registersPeter Maydell2014-08-191-14/+20
* target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14Peter Maydell2014-08-191-3/+8
* target-arm: Collect up the debug cp register definitionsPeter Maydell2014-08-191-32/+53
* target-arm: Fix return address for A64 BRK instructionsPeter Maydell2014-08-191-1/+1
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