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* build: kill libdis, move disassemblers to disas/Paolo Bonzini2012-12-191-1/+1
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin2012-12-081-3/+3
| | | | | Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin2012-12-081-1/+1
| | | | | Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin2012-12-081-2/+2
| | | | | Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin2012-11-171-3/+3
| | | | | | Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin2012-11-171-4/+4
| | | | | | Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* disas: avoid using cpu_single_envBlue Swirl2012-11-101-1/+1
| | | | | | | | | Pass around CPUArchState instead of using global cpu_single_env. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Richard Henderson <rth@twiddle.net> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
* target-arm: Implement abs_i32 inline rather than as a helperPeter Maydell2012-10-241-2/+9
| | | | | | | | Implement abs_i32 inline (with movcond) rather than using a helper function. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Use TCG operation for Neon 64 bit negationPeter Maydell2012-10-241-1/+3
| | | | | | | | Use the TCG operation to do Neon 64 bit negations rather than calling a helper routine for it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm/translate: Fix RRX operandsPeter Crosthwaite2012-10-171-1/+1
| | | | | | | | | | | | | | | | | | Instructions that both use the RRX second operand and update CS were incorrect, as the Carry flag was updated too early. An example of such an instruction would be: ands r12,r13,RRX Ands, because of the "s" flag will update the carry flag. But the RRX second operand rotates through the C flag which should happen before the update. Fixed the ordering of the two, the old carry is read by "r13,RRX" before being updated. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reported-by: Vinesh Peringat <vineshp@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: use deposit instead of hardcoded versionAurelien Jarno2012-10-051-14/+6
| | | | | | | | Use the deposit op instead of and hardcoded bit field insertion. It allows the host to emit the corresponding instruction if available. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: convert sar, shl and shr helpers to TCGAurelien Jarno2012-10-051-6/+43
| | | | | | | | | | | Now that the movcond TCG op is available, it's possible to replace shl and shr helpers by TCG code. The code generated by TCG is slightly longer than the code generated by GCC for the helper but is still worth it as this avoid all the consequences of using an helper: globals saved back to memory, no possible optimization, call overhead, etc. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: convert add_cc and sub_cc helpers to TCGAurelien Jarno2012-10-051-18/+48
| | | | | | | | | | | Now that the setcond TCG op is available, it's possible to replace add_cc and sub_cc helpers by TCG code. The code generated by TCG is actually very close to the one generated by GCC for the helper, and this avoid all the consequences of using an helper: globals saved back to memory, no possible optimization, call overhead, etc. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: use globals for CC flagsAurelien Jarno2012-10-051-81/+46
| | | | | | | | | Use globals for CC flags instead of loading/storing them each they are accessed. This allows some optimizations to be performed by the TCG optimization passes. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Reinstate display of VFP registers in cpu_dump_statePeter Maydell2012-10-051-26/+16
| | | | | | | | | | | Reinstate the display of VFP registers in cpu_dump_state(), if the CPU has them (this code had been #if 0'd out a for a long time). We drop the attempt ot display the values as floating point, since this makes assumptions about the host 'float' and 'double' formats and is not done by eg the i386 cpu_dump_state(). This display is gated on the CPU_DUMP_FPU flag, as for x86. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson2012-09-271-1/+1
| | | | | | | | | | | For all targets that currently call tcg_gen_debug_insn_start, add CPU_LOG_TB_OP_OPT to the condition that gates it. This is useful for comparing optimization dumps, when the pre-optimization dump is merely noise. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: final conversion to AREG0 free modeBlue Swirl2012-09-151-3/+3
| | | | | | | Convert code load functions and switch to AREG0 free mode. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: convert remaining helpersBlue Swirl2012-09-151-67/+67
| | | | | | | | Convert remaining helpers to AREG0 free mode: add an explicit CPUState parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: convert void helpersBlue Swirl2012-09-151-4/+4
| | | | | | | | | Add an explicit CPUState parameter instead of relying on AREG0. For easier review, convert only op helpers which don't return any value. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Fix typos in commentsPeter Maydell2012-08-101-5/+5
| | | | | | | | Fix a variety of typos in comments in target-arm files. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* arm: translate: comment typo - s/middel/middle/Peter A. G. Crosthwaite2012-08-101-1/+1
| | | | | | | Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* target-arm: Fix TCG temp handling in 64 bit cp writesPeter Maydell2012-07-121-0/+2
| | | | | | | | | | | | Fix errors in the TCG temp handling in the 64 bit coprocessor write path: we were reusing a 32 bit temp after it had been freed by store_reg(), and failing to free a 64 bit temp. This bug has no visible effect at this point because there aren't any non-NOP 64 bit registers yet; it needs to be fixed as a prerequisite for the 64 bit registers in LPAE support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Fix CP15 based WFIPaul Brook2012-07-121-1/+1
| | | | | | | | | | | The coprocessor register rework broke cp15 based WFI instructions. We incorrectly fall through the normal register write case, which incorrectly adds a forced block termination. We've already done a special version of this (DISAS_WFI), so return immediately. Signed-off-by: Paul Brook <paul@codesourcery.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Remove remaining old cp15 infrastructurePeter Maydell2012-06-201-58/+1
| | | | | | | There are now no uses of the old cp15 infrastructure, so it can be deleted. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Move block cache ops to new cp15 frameworkPeter Maydell2012-06-201-6/+1
| | | | | | | | | Move the v6 optional block cache ops to the new cp15 framework. This includes only providing them on the CPUs which implemented them, rather than the previous blunderbuss approach of making all MCRR instructions on all CPUs act as NOPs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert performance monitor registersPeter Maydell2012-06-201-25/+1
| | | | | | | Convert the v7 performance monitor cp15 registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert TLS registersPeter Maydell2012-06-201-58/+0
| | | | | | Convert TLS registers to the new cp15 framework Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert WFI/barriers special cases to cp_reginfoPeter Maydell2012-06-201-51/+0
| | | | | | | Convert the various WFI and barrier instruction special cases to use cp_reginfo infrastructure. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert TEECR, TEEHBR to new schemePeter Maydell2012-06-201-66/+0
| | | | | | | Convert the THUMB2EE cp14 registers TEECR and TEEHBR to use arm_cp_reginfo. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert debug registers to cp_reginfoPeter Maydell2012-06-201-28/+0
| | | | | | | Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to the cp_reginfo scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Remove old cpu_arm_set_cp_io infrastructurePeter Maydell2012-06-201-40/+1
| | | | | | | All the users of cpu_arm_set_cp_io have been converted, so we can remove it and the infrastructure it used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: initial coprocessor register frameworkPeter Maydell2012-06-201-1/+155
| | | | | | | | | | Initial infrastructure for data-driven registration of coprocessor register implementations. We still fall back to the old-style switch statements pending complete conversion of all existing registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Make SETEND respect bswap_code (BE8) settingPeter Maydell2012-04-271-4/+4
| | | | | | | | | | | | Make the SETEND instruction respect the setting of bswap_code, so that in BE8 mode we UNDEF for attempts to switch into little-endian mode and nop for attempts to stay in big-endian mode. (This is the inverse of the existing handling of SETEND in the more common little-endian setup, which we use since we don't implement the architecturally-mandated dynamic endianness switching.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Userspace ARM BE8 supportPaul Brook2012-04-061-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for ARM BE8 userspace binaries. i.e. big-endian data and little-endian code. In principle LE8 mode is also possible, but AFAIK has never actually been implemented/used. System emulation doesn't have any useable big-endian board models, but should in principle work once you fix that. Dynamic endianness switching requires messing with data accesses, preferably with TCG cooperation, and is orthogonal to BE8 support. Signed-off-by: Paul Brook <paul@codesourcery.com> [PMM: various changes, mostly as per my suggestions in code review: * rebase * use EF_ defines rather than hardcoded constants * make bswap_code a bool for future VMSTATE macro compatibility * update comment in cpu.h about TB flags bit field usage * factor out load-code-and-swap into arm_ld*_code functions and get_user_code* macros * fix stray trailing space at end of line * added braces in disas.c to satisfy checkpatch ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
* ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers.Andrew Towers2012-03-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | This patch replaces the ARM_FEATURE_VFP3 test when reading MVFR registers with a test for a new feature flag ARM_FEATURE_MVFR, and sets this feature for all ARMv6K cores (ARM1156 is not a v6K core, yet supports MVFR; qemu does not support ARM1156 at this time.) MVFR0 and MVFR1 were introduced in ARM1136JF-S r1p0 (ARMv6K, VFPv2) and are present in ARM1156T2F-S (non-v6K), ARM1176JZF-S, ARM11MPCore and newer cores. Reference: ARM DDI 0211H, 0290G, 0301H, 0360E. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0211h/Ffbefjag.html Without this change, the linux kernel will not boot with VFP support enabled under ARM1176 system emulation, due to the unconditional use of MVFR1 at the end of vfp_init() in arch/arm/vfp/vfpmodule.c: VFP support v0.3: implemetor 41 architecture 1 part 20 variant b rev 5 Internal error: Oops - undefined instruction: 0 [#1] Signed-off-by: Andrew Towers <atowers@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Decode SETEND correctly in ThumbPeter Maydell2012-03-151-23/+40
| | | | | | | | | | | | | | Decode the SETEND instruction correctly in Thumb mode, rather than accidentally treating it like CPS. We don't support BE8 mode, but this change brings the Thumb mode in to line with behaviour in ARM mode: 'SETEND BE' is not supported and will provoke an UNDEF exception, but 'SETEND LE' is correctly handled as a no-op. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reported-by: Daniel Forsgren <daniel.forsgren@enea.com> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
* target-arm: Don't overuse CPUStateAndreas Färber2012-03-141-52/+52
| | | | | | | | | | Scripted conversion: sed -i "s/CPUState/CPUARMState/g" target-arm/*.[hc] sed -i "s/#define CPUARMState/#define CPUState/" target-arm/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com> Acked-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Fix errors in decode of M profile CPSPeter Maydell2012-01-131-4/+4
| | | | | | | | | | | Fix errors in the decode of M profile CPS: * the decode of the I (affects PRIMASK) and F (affects FAULTMASK) bits was reversed * the FAULTMASK system register number is 19, not 17 This fixes an issue reported as LP:913925. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm/translate.c: Fix slightly misleading comment in Thumb decoderPeter Maydell2011-12-051-3/+5
| | | | | | | | | | Clarify some slightly misleading comments in the Thumb decoder's handling of the memory hint space -- in particular one code path marked as 'UNPREDICTABLE or unallocated hint' also includes some legitimate preload instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* target-arm: Implement VFPv4 fused multiply-accumulate insnsPeter Maydell2011-10-191-0/+72
| | | | | | | Implement the fused multiply-accumulate instructions (VFMA, VFMS, VFNMA, VFNMS) which are new in VFPv4. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add ARM UDIV/SDIV supportPeter Maydell2011-10-191-0/+19
| | | | | | | | Add support for UDIV and SDIV in ARM mode. This is a new optional feature for A profile cores (Thumb mode has had UDIV and SDIV for M profile cores for some time). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIVPeter Maydell2011-10-191-1/+2
| | | | | | | | | | Rename the ARM_FEATURE_DIV feature bit to _THUMB_DIV, to make room for a new feature switch enabling DIV in the ARM encoding. (Cores may implement either (a) no divide insns (b) divide insns in Thumb encodings only (c) divide insns in both ARM and Thumb encodings.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: v6 media multiply space: UNDEF on unassigned encodingsPeter Maydell2011-10-191-4/+20
| | | | | | | | Clean up the decoding of the v6 media multiply space so that we UNDEF on unassigned encodings rather than randomly interpreting them as some instruction in this space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Don't print debug messages for various UNDEF casesPeter Maydell2011-07-261-6/+0
| | | | | | | | Remove some stray printfs for cases which don't generally happen (some VFP UNDEF cases, reads and writes to unknown cp14 registers); we should simply generate an UNDEF when the instruction is executed. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: UNDEF on a VCVTT/VCVTB UNPREDICTABLE to avoid TCG assertPeter Maydell2011-07-261-8/+11
| | | | | | | | | | | VCVTT/VCVTB with bit 8 set is UNPREDICTABLE; we choose to UNDEF. This avoids a TCG assert later when the VCVTT/VCVTB code tries to use a source register that wasn't ever set up. We pull the check for the presence of the half-precision extension up in to this common code as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Handle UNDEF and UNPREDICTABLE cases for VLDM, VSTMPeter Maydell2011-07-261-7/+31
| | | | | | | | Handle the UNDEF and UNPREDICTABLE cases for VLDM and VSTM. In particular, we now generate an undef exception for overlarge imm8 values rather than generating 1000+ TCG ops and hitting an assertion. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Support v6 barriers in linux-user modePeter Maydell2011-07-261-18/+33
| | | | | | | | | | | | | | ARMv6 implemented various operations as special cases of cp15 accesses which are true instructions in v7; this includes barriers (DMB, DSB, ISB). Catch this special case at translate time, so that it works in linux-user mode (which doesn't provide a functional get_cp15 helper) as well as system mode. Includes minor cleanup of the existing cases (single switch statement, and doing the "OK in user mode?" test explicitly rather than hiding it in cp15_user_ok()). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge branch 'for-upstream' of git://git.linaro.org/people/pmaydell/qemu-armBlue Swirl2011-07-201-177/+280
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: target-arm: Fix BASEPRI, BASEPRI_MAX, and FAULTMASK access target-arm: Minimal implementation of performance counters Revert "Makefile.target: Allow target helpers to be in any *_helper.c file" Revert "target-arm: Use global env in neon_helper.c helpers" target-arm: Pass fp status pointer explicitly to neon fp helpers target-arm: Make VFP binop helpers take pointer to fpstatus, not CPUState target-arm: Add helper function to generate code to get fpstatus pointer Revert "target-arm: Use global env in iwmmxt_helper.c helpers" Conflicts: Makefile.target
| * target-arm: Minimal implementation of performance countersPeter Maydell2011-06-221-2/+18
| | | | | | | | | | | | | | | | | | Newer Linux kernels assume the existence of the performance counter cp15 registers. Provide a minimal implementation of these registers. We support no events. This should be compliant with the ARM ARM, except that we don't implement the cycle counter. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * Revert "target-arm: Use global env in neon_helper.c helpers"Peter Maydell2011-06-221-54/+86
| | | | | | | | | | | | | | | | | | This effectively reverts commit 2a3f75b42ac255be09ec2939b96c549ec830efd3 so that we return to passing CPUState to helpers as an explicit parameter. (There were a number of conflicts in target-arm/translate.c which had to be resolved by hand so it is not a pure revert.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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