| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | tcg: Invert the inclusion of helper.h | Richard Henderson | 2014-05-28 | 1 | -3/+2 |
| * | target-arm: Add SPSR entries for EL2/HYP and EL3/MON | Edgar E. Iglesias | 2014-05-27 | 1 | -2/+2 |
| * | target-arm: A32: Use get_mem_index for load/stores | Edgar E. Iglesias | 2014-05-27 | 1 | -106/+106 |
| * | target-arm/translate.c: Use get_mem_index() for SRS memory accesses | Peter Maydell | 2014-05-27 | 1 | -2/+2 |
| * | target-arm/translate.c: Clean up mmu index handling for ldrt/strt | Peter Maydell | 2014-05-27 | 1 | -12/+17 |
| * | arm: translate.c: Fix smlald Instruction | Peter Crosthwaite | 2014-04-17 | 1 | -11/+23 |
| * | target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32 | Peter Maydell | 2014-04-17 | 1 | -0/+5 |
| * | target-arm: Implement ARMv8 MVFR registers | Peter Maydell | 2014-04-17 | 1 | -2/+8 |
| * | target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1 | Peter Maydell | 2014-04-17 | 1 | -0/+31 |
| * | target-arm: Add support for generating exceptions with syndrome information | Peter Maydell | 2014-04-17 | 1 | -38/+65 |
| * | target-arm: Provide correct syndrome information for cpreg access traps | Peter Maydell | 2014-04-17 | 1 | -1/+44 |
| * | target-arm: Split out private-to-target functions into internals.h | Peter Maydell | 2014-04-17 | 1 | -0/+1 |
| * | target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate) | Alex Bennée | 2014-03-17 | 1 | -2/+10 |
| * | target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE | Alex Bennée | 2014-03-17 | 1 | -2/+10 |
| * | target-arm: A64: Implement PMULL instruction | Peter Maydell | 2014-03-17 | 1 | -0/+1 |
| * | exec: Change cpu_abort() argument to CPUState | Andreas Färber | 2014-03-13 | 1 | -1/+1 |
| * | cpu: Move breakpoints field from CPU_COMMON to CPUState | Andreas Färber | 2014-03-13 | 1 | -2/+2 |
| * | target-arm: Implement WFE as a yield operation | Peter Maydell | 2014-03-10 | 1 | -0/+6 |
| * | target-arm: Add support for AArch32 ARMv8 CRC32 instructions | Will Newton | 2014-02-26 | 1 | -0/+56 |
| * | target-arm: Remove unnecessary code now read/write fns can't fail | Peter Maydell | 2014-02-20 | 1 | -4/+0 |
| * | target-arm: Split cpreg access checks out from read/write functions | Peter Maydell | 2014-02-20 | 1 | -0/+11 |
| * | target-arm: Log bad system register accesses with LOG_UNIMP | Peter Maydell | 2014-02-20 | 1 | -0/+13 |
| * | target-arm: Add support for AArch32 64bit VCVTB and VCVTT | Will Newton | 2014-02-08 | 1 | -22/+61 |
| * | target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM | Will Newton | 2014-01-31 | 1 | -1/+52 |
| * | target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM | Will Newton | 2014-01-31 | 1 | -0/+61 |
| * | target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ | Will Newton | 2014-01-31 | 1 | -1/+39 |
| * | target-arm: Add support for AArch32 SIMD VRINTX | Will Newton | 2014-01-31 | 1 | -1/+10 |
| * | target-arm: Add support for AArch32 FP VRINTX | Will Newton | 2014-01-31 | 1 | -0/+11 |
| * | target-arm: Add support for AArch32 FP VRINTZ | Will Newton | 2014-01-31 | 1 | -0/+16 |
| * | target-arm: Add support for AArch32 FP VRINTR | Will Newton | 2014-01-31 | 1 | -0/+11 |
| * | target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM | Will Newton | 2014-01-31 | 1 | -0/+54 |
| * | target-arm: Rename A32 VFP conversion helpers | Will Newton | 2014-01-08 | 1 | -11/+13 |
| * | target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum | Peter Maydell | 2014-01-08 | 1 | -8/+8 |
| * | target-arm: Widen exclusive-access support struct fields to 64 bits | Peter Maydell | 2014-01-08 | 1 | -26/+39 |
| * | target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder | Peter Maydell | 2014-01-07 | 1 | -3/+4 |
| * | target-arm: A64: add support for conditional branches | Alexander Graf | 2013-12-17 | 1 | -5/+9 |
| * | target-arm: Split A64 from A32/T32 gen_intermediate_code_internal() | Peter Maydell | 2013-12-17 | 1 | -38/+24 |
| * | target-arm: add support for v8 AES instructions | Ard Biesheuvel | 2013-12-17 | 1 | -0/+26 |
| * | target-arm: Use new qemu_ld/st opcodes | Richard Henderson | 2013-12-10 | 1 | -31/+25 |
| * | target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions. | Will Newton | 2013-12-10 | 1 | -9/+22 |
| * | target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions. | Will Newton | 2013-12-10 | 1 | -0/+50 |
| * | target-arm: Implement ARMv8 VSEL instruction. | Will Newton | 2013-12-10 | 1 | -1/+134 |
| * | target-arm: Move call to disas_vfp_insn out of disas_coproc_insn. | Will Newton | 2013-12-10 | 1 | -5/+27 |
| * | tcg: Move helper registration into tcg_context_init | Richard Henderson | 2013-10-10 | 1 | -3/+0 |
| * | target-arm: Add AArch64 translation stub | Alexander Graf | 2013-09-10 | 1 | -3/+11 |
| * | target-arm: Prepare translation for AArch64 code | Alexander Graf | 2013-09-10 | 1 | -9/+29 |
| * | target-arm: Pass DisasContext* to gen_set_pc_im() | Peter Maydell | 2013-09-10 | 1 | -13/+13 |
| * | target-arm: Fix target_ulong/uint32_t confusions | Alexander Graf | 2013-09-10 | 1 | -4/+5 |
| * | target-arm: Export cpu_env | Alexander Graf | 2013-09-10 | 1 | -1/+1 |
| * | target-arm: Extract the disas struct to a header file | Alexander Graf | 2013-09-10 | 1 | -23/+1 |
