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path: root/target-arm/translate.c
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* target-arm: Add support for AArch32 ARMv8 CRC32 instructionsWill Newton2014-02-261-0/+56
* target-arm: Remove unnecessary code now read/write fns can't failPeter Maydell2014-02-201-4/+0
* target-arm: Split cpreg access checks out from read/write functionsPeter Maydell2014-02-201-0/+11
* target-arm: Log bad system register accesses with LOG_UNIMPPeter Maydell2014-02-201-0/+13
* target-arm: Add support for AArch32 64bit VCVTB and VCVTTWill Newton2014-02-081-22/+61
* target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTMWill Newton2014-01-311-1/+52
* target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTMWill Newton2014-01-311-0/+61
* target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZWill Newton2014-01-311-1/+39
* target-arm: Add support for AArch32 SIMD VRINTXWill Newton2014-01-311-1/+10
* target-arm: Add support for AArch32 FP VRINTXWill Newton2014-01-311-0/+11
* target-arm: Add support for AArch32 FP VRINTZWill Newton2014-01-311-0/+16
* target-arm: Add support for AArch32 FP VRINTRWill Newton2014-01-311-0/+11
* target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTMWill Newton2014-01-311-0/+54
* target-arm: Rename A32 VFP conversion helpersWill Newton2014-01-081-11/+13
* target-arm: Use VFP_BINOP macro for min, max, minnum, maxnumPeter Maydell2014-01-081-8/+8
* target-arm: Widen exclusive-access support struct fields to 64 bitsPeter Maydell2014-01-081-26/+39
* target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoderPeter Maydell2014-01-071-3/+4
* target-arm: A64: add support for conditional branchesAlexander Graf2013-12-171-5/+9
* target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()Peter Maydell2013-12-171-38/+24
* target-arm: add support for v8 AES instructionsArd Biesheuvel2013-12-171-0/+26
* target-arm: Use new qemu_ld/st opcodesRichard Henderson2013-12-101-31/+25
* target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions.Will Newton2013-12-101-9/+22
* target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions.Will Newton2013-12-101-0/+50
* target-arm: Implement ARMv8 VSEL instruction.Will Newton2013-12-101-1/+134
* target-arm: Move call to disas_vfp_insn out of disas_coproc_insn.Will Newton2013-12-101-5/+27
* tcg: Move helper registration into tcg_context_initRichard Henderson2013-10-101-3/+0
* target-arm: Add AArch64 translation stubAlexander Graf2013-09-101-3/+11
* target-arm: Prepare translation for AArch64 codeAlexander Graf2013-09-101-9/+29
* target-arm: Pass DisasContext* to gen_set_pc_im()Peter Maydell2013-09-101-13/+13
* target-arm: Fix target_ulong/uint32_t confusionsAlexander Graf2013-09-101-4/+5
* target-arm: Export cpu_envAlexander Graf2013-09-101-1/+1
* target-arm: Extract the disas struct to a header fileAlexander Graf2013-09-101-23/+1
* target-arm: Abstract out load/store from a vaddr in AArch32Peter Maydell2013-09-101-124/+210
* target-arm: Use sextract32() in branch decodePeter Maydell2013-09-101-2/+3
* Merge remote-tracking branch 'mjt/trivial-patches' into stagingAnthony Liguori2013-09-031-0/+4
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| * target-arm: Report unimplemented opcodes (LOG_UNIMP)Stefan Weil2013-09-011-0/+4
* | tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson2013-09-021-1/+1
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* target-arm: Support coprocessor registers which do I/OPeter Maydell2013-08-201-3/+13
* cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber2013-07-231-3/+4
* target-arm: explicitly decode SEVL instructionMans Rullgard2013-07-151-1/+2
* target-arm: implement LDA/STL instructionsMans Rullgard2013-07-151-10/+119
* target-arm: add feature flag for ARMv8Mans Rullgard2013-07-151-0/+1
* target-arm: Change gen_intermediate_code_internal() argument to ARMCPUAndreas Färber2013-07-091-4/+5
* cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber2013-06-281-2/+4
* Merge remote-tracking branch 'pmaydell/target-arm.next' into stagingAnthony Liguori2013-06-141-1/+1
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| * Fix rfe instructionPeter Chubb2013-06-031-1/+1
* | Remove unnecessary break statementsStefan Weil2013-06-011-1/+0
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* target-arm: Remove gen_{ld,st}* definitionsPeter Maydell2013-05-261-46/+0
* target-arm: Remove gen_{ld,st}* from thumb2 decoderPeter Maydell2013-05-261-10/+20
* target-arm: Remove gen_{ld,st}* from Thumb insnsPeter Maydell2013-05-261-25/+46
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