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path: root/target-arm/translate.c
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* target-*: Advance pc after recognizing a breakpointRichard Henderson2015-10-281-2/+5
* target-arm/translate.c: Handle non-executable page-straddling Thumb insnsPeter Maydell2015-10-271-1/+44
* target-arm: Fix CPU breakpoint handlingSergey Fedorov2015-10-161-5/+14
* target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin2015-10-161-2/+15
* tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-071-45/+9
* tcg: Pass data argument to restore_state_to_opcRichard Henderson2015-10-071-4/+5
* tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-071-1/+5
* target-arm: Add condexec state to insn_startRichard Henderson2015-10-071-1/+2
* target-*: Introduce and use cpu_breakpoint_testRichard Henderson2015-10-071-15/+16
* target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson2015-10-071-3/+4
* target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson2015-10-071-4/+1
* tcg: Rename debug_insn_start to insn_startRichard Henderson2015-10-071-1/+1
* target-arm: Handle always condition codes within arm_test_ccRichard Henderson2015-09-141-0/+9
* target-arm: Introduce DisasCompareRichard Henderson2015-09-141-46/+69
* target-arm: Share all common TCG temporariesRichard Henderson2015-09-141-5/+5
* maint: remove / fix many doubled wordsDaniel P. Berrange2015-09-111-1/+1
* target-arm: Fix default_exception_el() function for the case when EL3 is not ...Sergey Sorokin2015-09-081-1/+5
* tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson2015-08-241-23/+23
* target-arm: Implement YIELD insn to yield in ARM and Thumb translatorsPeter Maydell2015-07-061-0/+7
* disas: Remove uses of CPU envPeter Crosthwaite2015-06-221-1/+1
* target-arm: Correct "preferred return address" for cpreg access exceptionsPeter Maydell2015-06-151-1/+1
* target-arm: Add the THUMB_DSP featureAurelio C. Remonda2015-06-151-10/+102
* target-arm: Avoid buffer overrun on UNPREDICTABLE ldrd/strdPeter Maydell2015-05-291-24/+32
* target-arm: Don't halt on WFI unless we don't have any workPeter Maydell2015-05-291-0/+4
* target-arm: Extend FP checks to use an ELGreg Bellows2015-05-291-10/+7
* target-arm: Add exception target el infrastructureGreg Bellows2015-05-291-23/+42
* target-arm: Fix handling of STM (user) with r15 in register listPeter Maydell2015-03-161-6/+12
* tcg: Change translator-side labels to a pointerRichard Henderson2015-03-131-4/+4
* tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-121-6/+3
* tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson2015-02-121-1/+0
* target-arm: Use correct mmu_idx for unprivileged loads and storesPeter Maydell2015-02-051-2/+24
* target-arm: Define correct mmu_idx values and pass them in TB flagsPeter Maydell2015-02-051-2/+3
* target-arm: check that LSB <= MSB in BFI instructionKirill Batuzov2015-02-051-0/+4
* gen-icount: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-1/+1
* translate: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-2/+2
* target-arm: add secure state bit to CPREG hashPeter Maydell2014-12-111-5/+9
* target-arm: add non-secure Translation Block flagSergey Fedorov2014-12-111-0/+1
* target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn()Peter Maydell2014-11-041-6/+5
* target-arm/translate.c: Don't pass CPUARMState around in the decoderPeter Maydell2014-11-041-44/+50
* target-arm/translate.c: Don't use IS_M()Peter Maydell2014-11-041-8/+11
* target-arm/translate.c: Use arm_dc_feature() rather than arm_feature()Peter Maydell2014-11-041-60/+80
* target-arm/translate.c: Use arm_dc_feature() in ENABLE_ARCH_ macrosPeter Maydell2014-11-041-8/+8
* target-arm: rename arm_current_pl to arm_current_elGreg Bellows2014-10-241-2/+2
* target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0Peter Maydell2014-10-241-0/+3
* target-arm: Add support for A32 and T32 HVC and SMC insnsPeter Maydell2014-10-241-11/+92
* target-arm: Don't handle c15_cpar changes via tb_flush()Peter Maydell2014-09-291-19/+21
* target-arm: Implement ARMv8 single-stepping for AArch32 codePeter Maydell2014-08-191-2/+74
* target-arm: Don't allow AArch32 to access RES0 CPSR bitsPeter Maydell2014-08-191-6/+7
* trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova2014-08-121-0/+3
* target-arm: Delete unused iwmmxt_msadb helperPeter Maydell2014-06-091-2/+0
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