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* | Remove unnecessary break statementsStefan Weil2013-06-011-1/+0
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* target-arm: Remove gen_{ld,st}* definitionsPeter Maydell2013-05-261-46/+0
* target-arm: Remove gen_{ld,st}* from thumb2 decoderPeter Maydell2013-05-261-10/+20
* target-arm: Remove gen_{ld,st}* from Thumb insnsPeter Maydell2013-05-261-25/+46
* target-arm: Remove gen_{ld,st}* from basic ARM insnsPeter Maydell2013-05-261-32/+69
* target-arm: Remove use of gen_{ld,st}* from ldrex/strexPeter Maydell2013-05-261-13/+18
* target-arm: Remove uses of gen_{ld,st}* from Neon codePeter Maydell2013-05-261-18/+28
* target-arm: Remove uses of gen_{ld,st}* from iWMMXt codePeter Maydell2013-05-261-8/+10
* target-arm: Remove gen_ld64() and gen_st64()Peter Maydell2013-05-261-15/+4
* target-arm: Don't use TCGv when we mean TCGv_i32Peter Maydell2013-05-261-224/+229
* target-arm: Reinsert missing return statement in ARM mode SRS decodePeter Chubb2013-04-191-0/+1
* target-arm: Don't decode RFE or SRS on M profile coresPeter Maydell2013-03-051-2/+3
* target-arm: Factor out handling of SRS instructionPeter Maydell2013-03-051-67/+69
* gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell2013-03-031-2/+2
* target-arm: Fix sbc_CC carryRichard Henderson2013-02-251-24/+4
* arm/translate.c: Fix adc_CC/sbc_CC implementationPeter Crosthwaite2013-02-251-2/+2
* target-arm: Implement sbc_cc inlineRichard Henderson2013-02-231-8/+39
* target-arm: Implement adc_cc inlineRichard Henderson2013-02-231-5/+34
* target-arm: Use add2 in gen_add_CCRichard Henderson2013-02-231-4/+3
* target-arm: Use mul[us]2 and add2 in umlal et alRichard Henderson2013-02-231-12/+14
* target-arm: Use mul[us]2 in gen_mul[us]_i64_i32Richard Henderson2013-02-231-16/+22
* target-arm: Fix TCG temp leaks for WI and UNDEF VFP sysreg writesPeter Maydell2013-01-301-1/+4
* misc: move include files to include/qemu/Paolo Bonzini2012-12-191-1/+1
* exec: move include files to include/exec/Paolo Bonzini2012-12-191-1/+1
* build: kill libdis, move disassemblers to disas/Paolo Bonzini2012-12-191-1/+1
* TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin2012-12-081-3/+3
* TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin2012-12-081-1/+1
* TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin2012-12-081-2/+2
* TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin2012-11-171-3/+3
* TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin2012-11-171-4/+4
* disas: avoid using cpu_single_envBlue Swirl2012-11-101-1/+1
* target-arm: Implement abs_i32 inline rather than as a helperPeter Maydell2012-10-241-2/+9
* target-arm: Use TCG operation for Neon 64 bit negationPeter Maydell2012-10-241-1/+3
* target-arm/translate: Fix RRX operandsPeter Crosthwaite2012-10-171-1/+1
* target-arm: use deposit instead of hardcoded versionAurelien Jarno2012-10-051-14/+6
* target-arm: convert sar, shl and shr helpers to TCGAurelien Jarno2012-10-051-6/+43
* target-arm: convert add_cc and sub_cc helpers to TCGAurelien Jarno2012-10-051-18/+48
* target-arm: use globals for CC flagsAurelien Jarno2012-10-051-81/+46
* target-arm: Reinstate display of VFP registers in cpu_dump_statePeter Maydell2012-10-051-26/+16
* Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson2012-09-271-1/+1
* target-arm: final conversion to AREG0 free modeBlue Swirl2012-09-151-3/+3
* target-arm: convert remaining helpersBlue Swirl2012-09-151-67/+67
* target-arm: convert void helpersBlue Swirl2012-09-151-4/+4
* target-arm: Fix typos in commentsPeter Maydell2012-08-101-5/+5
* arm: translate: comment typo - s/middel/middle/Peter A. G. Crosthwaite2012-08-101-1/+1
* target-arm: Fix TCG temp handling in 64 bit cp writesPeter Maydell2012-07-121-0/+2
* target-arm: Fix CP15 based WFIPaul Brook2012-07-121-1/+1
* target-arm: Remove remaining old cp15 infrastructurePeter Maydell2012-06-201-58/+1
* target-arm: Move block cache ops to new cp15 frameworkPeter Maydell2012-06-201-6/+1
* target-arm: Convert performance monitor registersPeter Maydell2012-06-201-25/+1
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