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* target-arm: Treat UNPREDICTABLE VTBL, VTBX case as UNDEFPeter Maydell2011-04-121-1/+8
| | | | | | | | | Catch the UNPREDICTABLE case for Neon VTBL,VTBX, and UNDEF it rather than allowing the helper function to index off the end of the register file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Handle UNDEF cases for Neon 2 register misc formsPeter Maydell2011-04-121-5/+16
| | | | | | | | | | | | | Add missing UNDEF checks for Neon "two register miscellaneous" forms: * all instructions except VMOVN,VQMOVN must UNDEF if Q==1 && (Vd<0> == 1 || Vm<0> == 1) * VMOVN,VQMOVN,VCVT.F16.F32 UNDEF if Q == 1 || Vm<0> == 1 * VSHLL,VCVT.F32.F16 UNDEF if Q == 1 || Vd<0> == 1 (The only other UNDEF case is VZIP,VUZP if Q == 0 && size == 10, which we already handle.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Simplify checking of size field in Neon 2reg-misc formsPeter Maydell2011-04-121-76/+179
| | | | | | | | | | | Many of the Neon "2 register misc" instruction forms require invalid size fields to cause the instruction to UNDEF. Pull this information out into an array; this simplifies the code and also means we can do the check early and avoid the problem of leaking TCG temporaries in the illegal_op case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Handle UNDEF cases for VEXTPeter Maydell2011-04-121-0/+4
| | | | | | | VEXT must UNDEF if Q == 1 && (Vd<0> == 1 || Vr<0> == 1 || Vm<0> == 1) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Handle UNDEF cases for Neon 2 regs + scalar formsPeter Maydell2011-04-121-10/+27
| | | | | | | | Add missing checks for cases which must UNDEF in the Neon "2 registers and a scalar" data processing instruction space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Handle UNDEF cases for Neon 3-regs-different-widthsPeter Maydell2011-04-121-20/+36
| | | | | | | | Add missing UNDEF checks for instructions in the Neon "3 registers of different widths" data processing space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Handle UNDEF cases for Neon invalid modified-immediatesPeter Maydell2011-04-121-0/+10
| | | | | | | | | | For Neon "one register and a modified immediate value" forms, the combination op=1 cmode=1111 is unallocated and should UNDEF. All instructions of this form also UNDEF if Q == 1 and Vd<0> == 1. We also add a comment on the only UNPREDICTABLE in this space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Collapse VSRI case into VSHL, VSLIPeter Maydell2011-04-121-4/+0
| | | | | | | | | | | Collapse some switch cases for VSRI into those for VSHL, VSLI, since the bodies are the same. (This is not completely obvious for the size < 3 case, but since for VSRI we know U=1 the GEN_NEON_INTEGER_OP() expansion is equivalent to the open-coded VSHL/VSLI case.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Handle UNDEF cases for Neon "2 regs and shift" insnsPeter Maydell2011-04-121-19/+22
| | | | | | | | | Correctly handle all the UNDEF cases for Neon instructions of the "2 registers and shift" form, and make sure that we check for these cases early enough not to leak TCG temporaries. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Simplify three-register pairwise codeJuha Riihimäki2011-04-121-11/+8
| | | | | | | | | | Since we know that the case of (pairwise && q) has been caught earlier, we can simplify the register setup code for each pass in the three-register-same-size Neon loop. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Handle UNDEF cases for Neon 3-regs-same insnsPeter Maydell2011-04-121-11/+43
| | | | | | | | | Correct the handling of UNDEF cases for the NEON "3 registers same size" forms, by adding missing checks and rationalising some others so they are done early enough to avoid leaking TCG temporaries. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Use lookup table for size check on Neon 3-reg-same insnsPeter Maydell2011-04-121-64/+133
| | | | | | | | | | | | Simplify the checks for invalid size values for the Neon "three registers of the same size" instruction forms (and add them where they were missing) by using a lookup table. This includes adding symbolic constants for the op values in this space, since we now use them in multiple places. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* arm: basic support for ARMv4/ARMv4T emulationDmitry Eremin-Solenikov2011-04-101-10/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently target-arm/ assumes at least ARMv5 core. Add support for handling also ARMv4/ARMv4T. This changes the following instructions: BX(v4T and later) BKPT, BLX, CDP2, CLZ, LDC2, LDRD, MCRR, MCRR2, MRRC, MCRR, MRC2, MRRC, MRRC2, PLD QADD, QDADD, QDSUB, QSUB, STRD, SMLAxy, SMLALxy, SMLAWxy, SMULxy, SMULWxy, STC2 (v5 and later) All instructions that are "v5TE and later" are also bound to just v5, as that's how it was before. This patch doesn _not_ include disabling of cp15 access and base-updated data abort model (that will be required to emulate chips based on a ARM7TDMI), because: * no ARM7TDMI chips are currently emulated (or planned) * those features aren't strictly necessary for my purposes (SA-1 core emulation). All v5 models are handled as they are v5T. Internally we still have a check if the model is a v5(T) or v5TE, but as all emulated cores are v5TE, those two cases are simply aliased (for now). Patch is heavily based on patch by Filip Navara <filip.navara@gmail.com> which in turn is based on work by Ulrich Hecht <uli@suse.de> and Vincent Sanders <vince@kyllikki.org>. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Fix conversions from pointer to tcg_target_longStefan Weil2011-04-101-1/+1
| | | | | | | | | | | | tcg_gen_exit_tb takes a parameter of type tcg_target_long, so the type casts of pointer to long should be replaced by type casts of pointer to tcg_target_long (suggested by Blue Swirl). These changes are needed for build environments where sizeof(long) != sizeof(void *), especially for w64. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Use global env in iwmmxt_helper.c helpersPeter Maydell2011-04-041-68/+61
| | | | | | | | Use the global 'env' variable in the helper functions in iwmmxt_helper.c. This means we don't need to pass env as an argument to them any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Use global env in neon_helper.c helpersPeter Maydell2011-04-041-65/+54
| | | | | | | | Use the global 'env' variable in the helper functions in neon_helper.c. This means we don't need to pass env as an argument to them any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Fix VCLE.F32 #0, VCLT.F32 #0 NaN handlingPeter Maydell2011-04-031-6/+12
| | | | | | | | | | Implementing the floating-point versions of VCLE #0 and VCLT #0 by doing a GT comparison and inverting the result gives the wrong result if the input is a NaN. Implement as a GT comparison with the operands swapped instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Don't leak TCG temp for UNDEFs in Neon load/store spacePeter Maydell2011-04-011-2/+6
| | | | | | | | | | Move the allocation and freeing of the TCG temp used for the address for Neon load/store instructions so that we don't allocate the temporary until we've done enough decoding to know that the instruction is not an UNDEF pattern; this avoids leaking the TCG temp in these cases. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Fix VLD of single element to all lanesPeter Maydell2011-04-011-25/+59
| | | | | | | | | | | | | | | | | Fix several bugs in VLD of single element to all lanes: The "single element to all lanes" form of VLD1 differs from those for VLD2, VLD3 and VLD4 in that bit 5 indicates whether the loaded element should be written to one or two Dregs (rather than being a register stride). Handle this by special-casing VLD1 rather than trying to have one loop which deals with both VLD1 and 2/3/4. Handle VLD4.32 with 16 byte alignment specified, rather than UNDEFfing. UNDEF for the invalid size and alignment combinations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Fix TCG temporary leaks for scalar VMULLPeter Maydell2011-03-221-0/+2
| | | | | | | Fix a TCG temporary leak when translating 32-bit scalar VMULL. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Set Q bit for overflow in SMUAD and SMLADPeter Maydell2011-03-221-4/+12
| | | | | | | | | | | | SMUAD and SMLAD are supposed to set the Q bit if the addition of the two 16x16 multiply products and optional accumulator overflows considered as a signed value. However we were only doing this check for the addition of the accumulator, not when adding the products, with the effect that we were mishandling the edge case where both inputs are 0x80008000. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Fix UNDEF cases in Thumb load/storePeter Maydell2011-03-221-11/+18
| | | | | | | | | | | | | | Decode of Thumb load/store was merging together the cases of 'bit 11==0' (reg+reg LSL imm) and 'bit 11==1' (reg+imm). This happens to work for valid instruction patterns but meant that we would not UNDEF for the cases the architecture mandates that we must. Make the decode actually look at bit 11 as well as [10..8] so that we UNDEF in the right places. This change also removes what was a spurious unreachable 'case 8', and correctly frees TCG temporaries on the illegal-insn codepaths. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Implement a minimal set of cp14 debug registersPeter Maydell2011-03-071-0/+28
| | | | | | | | | | | | | | Newer ARM kernels try to probe for whether the CPU has hardware breakpoint support. For this to work QEMU has to implement a minimal set of the cp14 debug registers. The architecture requires v7 cores to implement debug and so there is no defined way to report its absence; however in practice returning a zero DBGDIDR (ie with a reserved value for "debug architecture version") should cause well-written hw debug users to do the right thing. We also implement DBGDRAR and DBGDSAR as RAZ, indicating no memory mapped debug components. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Use TCG temporary leak debugging facilitiesPeter Maydell2011-03-071-0/+7
| | | | | | | | Use the new TCG temporary leak debugging facilities to check that each ARM instruction does not leak temporaries. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Remove ad-hoc leak checking codePeter Maydell2011-03-071-360/+338
| | | | | | | | | | This commit removes the ad-hoc resource leak checking code from target-arm. This includes replacing all uses of new_tmp() with tcg_temp_new_i32() and all uses of dead_tmp() with tcg_temp_free_i32(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Set carry flag correctly for Thumb2 ORNSPeter Maydell2011-03-061-2/+1
| | | | | | | | | | | The code for Thumb2 ORNS (or negated and set flags) was trashing a TCG input register which was needed later for use in calculating flags, with the effect that the carry flag was always set with the wrong sense. Fix this by using the TCG orc op instead of separate not and or ops. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Handle VMOV between two core and VFP single regsPeter Maydell2011-03-061-5/+5
| | | | | | | | | | | | | | | Fix two bugs in the translation of the instructions VMOV sa,sb,rx,ry and VMOV rx,ry,sa,sb (which copy between a pair of ARM core registers and a pair of VFP single precision registers): * An incorrect condition meant these instruction patterns were being treated as load/store multiple, which resulted in the generation of bad code and a runtime segfault * The order of the core register pair was reversed so the values would go to the wrong registers Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Don't decode old cp15 WFI instructions on v7 coresPeter Maydell2011-03-061-5/+30
| | | | | | | | | | | | | In v7 of the ARM architecture, WFI (wait for interrupt) is a first-class instruction, but in previous versions this functionality was provided via a cp15 coprocessor register. Add correct feature checks to the decoding of the cp15 WFI instructions so that they behave correctly for newer cores. In particular, the old 0,c7,c8,2 encoding used on ARM940 has been reused for VA-to-PA translation in v6 and v7. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Fix shift by immediate and narrow where src, dest overlapPeter Maydell2011-02-211-40/+44
| | | | | | | | | | | | | | For Neon shifts by immediate and narrow, correctly handle the case where the source registers and the destination registers overlap (the second pass should use the original register contents, not the results of the first pass). This includes a refactoring to pull the size check outside the loop rather than inside, since there is now very little common code between the size == 3 and size != 3 case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Refactor to pull narrowing decode into separate functionPeter Maydell2011-02-211-26/+19
| | | | | | | | Pull the code which decodes narrowing operations as being either signed/unsigned saturate or plain out into its own function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: fix decoding of Neon 64 bit shifts.Christophe Lyon2011-02-201-15/+30
| | | | | | | | | | Fix decoding of 64 bits variants of VSHRN, VRSHRN, VQSHRN, VQSHRUN, VQRSHRN, VQRSHRUN, taking into account whether inputs are unsigned or not. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: fix Neon VQSHRN and VSHRN.Christophe Lyon2011-02-201-2/+2
| | | | | | | | Call the normal shift helpers instead of the rounding ones. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Move Neon VZIP to helper functionsPeter Maydell2011-02-201-73/+36
| | | | | | | | | | Move the implementation of the Neon VUZP unzip instruction from inline code to helper functions. (At 50+ TCG ops it was well over the recommended limit for coding inline.) The helper implementations also give the correct answers where the inline implementation did not. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Move Neon VUZP to helper functionsPeter Maydell2011-02-201-75/+37
| | | | | | | | | | Move the implementation of the Neon VUZP unzip instruction from inline code to helper functions. (At 50+ TCG ops it was well over the recommended limit for coding inline.) The helper implementations also fix the handling of the quadword version of the instruction. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Correct conversion of Thumb Neon dp encodings into ARMJuha Riihimäki2011-02-201-1/+1
| | | | | | | | | | | | | We handle Thumb Neon data processing instructions by converting them into the equivalent ARM encoding, as the two are very close. However the ARM encoding should have bit 28 set, not clear. This wasn't causing any problems because we don't actually look at that bit during decode; however it is better to do the conversion correctly to avoid problems later if we add checks to UNDEF on SBZ/SBO bits. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Fix Neon VQDMLSL instructionPeter Maydell2011-02-201-8/+14
| | | | | | | For VQDMLSL, negation has to occur after saturation, not before. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Refactor handling of VQDMULLPeter Maydell2011-02-201-10/+6
| | | | | | | | | Refactor the handling of VQDMULL so that it is dealt with in its own if() case rather than together with the accumulating instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Implement VMULL.P8Peter Maydell2011-02-201-2/+4
| | | | | | | | Implement VMULL.P8 (the 32x32->64 version of the polynomial multiply instruction). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Use standard FPSCR for Neon half-precision operationsPeter Maydell2011-02-101-8/+8
| | | | | | | | | The Neon half-precision conversion operations (VCVT.F16.F32 and VCVT.F32.F16) use ARM standard floating-point arithmetic, unlike the VFP versions (VCVTB and VCVTT). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: implement vsli.64, vsri.64Christophe Lyon2011-02-091-1/+13
| | | | | | Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: fix VSHLL Neon instruction.Christophe Lyon2011-02-091-3/+15
| | | | | | | | Fix bit mask used when widening the result of shift on narrow input. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Fix VQMOVUN Neon instruction.Juha Riihimäki2011-02-091-6/+22
| | | | | | | | | | | VQMOVUN does a signed-to-unsigned saturating conversion. This is different from both the signed-to-signed and unsigned-to-unsigned conversions already implemented, so we need a new set of helper functions (neon_unarrow_sat*). Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Fix decoding of Thumb preload and hint spacePeter Maydell2011-02-041-22/+48
| | | | | | | | | | | Refine the decoding of the Thumb preload and hint space, so we UNDEF on the patterns that are supposed to UNDEF rather than NOP. We also move the tests for this space earlier, so we don't emit harmless but unnecessary address generation code for preload hints (which by their nature are likely to be in hot code paths). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Fix decoding of preload and memory hint spacePeter Maydell2011-02-041-3/+25
| | | | | | | | | | | Correct the decoding of the ARM preload and memory hint space, by adding decoding of PLI, PLDW and the v7MP unallocated hint space. This commit also corrects a slightly overexuberant decoding of PLD(register) which was not checking that bit 4 was one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Set the right overflow bit for neon 32 and 64 bit saturating add/sub.Christophe Lyon2011-02-041-10/+8
| | | | | | Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Fix Neon vsra instructions.Christophe Lyon2011-02-041-2/+2
| | | | | | | | This patch fixes the errors reported by my tests in VSRA. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Fix loading of scalar value for Neon multiply-by-scalarPeter Maydell2011-01-261-6/+6
| | | | | | | | | Fix the register and part of register we get the scalar from in the various "multiply vector by scalar" ops (VMUL by scalar and friends). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Fix garbage collection of temporaries in Neon emulation.Christophe Lyon2011-01-261-5/+13
| | | | | | | | Fix garbage collection of temporaries in Neon emulation. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Support saturation with shift=0.Christophe Lyon2011-01-261-16/+12
| | | | | | | | | | | This patch fixes corner-case saturations, when the target range is zero. It merely removes the guard against (sh == 0), and makes: __ssat(0x87654321, 1) return 0xffffffff and set the saturation flag __usat(0x87654321, 0) return 0 and set the saturation flag Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: Log instruction start in TCG codePeter Maydell2011-01-181-0/+4
| | | | | | | | Add support for logging the start of instructions in TCG code debug dumps for ARM targets. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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