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target-arm
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translate-a64.c
Commit message (
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)
Author
Age
Files
Lines
*
target-arm: A64: Implement unprivileged load/store
Peter Maydell
2014-02-20
1
-32
/
+37
*
target-arm: A64: Implement narrowing three-reg-diff operations
Peter Maydell
2014-02-20
1
-1
/
+59
*
target-arm: A64: Implement the wide 3-reg-different operations
Peter Maydell
2014-02-20
1
-1
/
+40
*
target-arm: A64: Add most remaining three-reg-diff widening ops
Peter Maydell
2014-02-20
1
-21
/
+88
*
target-arm: A64: Add opcode comments to disas_simd_three_reg_diff
Peter Maydell
2014-02-20
1
-11
/
+11
*
target-arm: A64: Implement store-exclusive for system mode
Peter Maydell
2014-02-20
1
-6
/
+62
*
target-arm: Remove unnecessary code now read/write fns can't fail
Peter Maydell
2014-02-20
1
-2
/
+0
*
target-arm: Split cpreg access checks out from read/write functions
Peter Maydell
2014-02-20
1
-0
/
+11
*
target-arm: Log bad system register accesses with LOG_UNIMP
Peter Maydell
2014-02-20
1
-1
/
+6
*
target-arm: A64: Implement remaining 3-same instructions
Peter Maydell
2014-02-20
1
-4
/
+48
*
target-arm: A64: Implement floating point pairwise insns
Alex Bennée
2014-02-20
1
-38
/
+86
*
target-arm: A64: Implement SIMD FP compare and set insns
Alex Bennée
2014-02-20
1
-12
/
+185
*
target-arm: A64: Implement scalar three different instructions
Peter Maydell
2014-02-20
1
-1
/
+94
*
target-arm: A64: Implement SIMD scalar indexed instructions
Peter Maydell
2014-02-20
1
-33
/
+82
*
target-arm: A64: Implement long vector x indexed insns
Peter Maydell
2014-02-20
1
-5
/
+139
*
target-arm: A64: Implement plain vector SIMD indexed element insns
Peter Maydell
2014-02-20
1
-1
/
+247
*
disas: Implement disassembly output for A64
Claudio Fontana
2014-02-08
1
-1
/
+1
*
target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group
Peter Maydell
2014-02-08
1
-3
/
+20
*
target-arm: A64: Add 2-reg-misc REV* instructions
Alex Bennée
2014-02-08
1
-1
/
+70
*
target-arm: A64: Add narrowing 2-reg-misc instructions
Peter Maydell
2014-02-08
1
-2
/
+83
*
target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT
Peter Maydell
2014-02-08
1
-6
/
+28
*
target-arm: A64: Implement 2-register misc compares, ABS, NEG
Peter Maydell
2014-02-08
1
-2
/
+134
*
target-arm: A64: Add skeleton decode for SIMD 2-reg misc group
Peter Maydell
2014-02-08
1
-1
/
+109
*
target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc
Peter Maydell
2014-02-08
1
-1
/
+86
*
target-arm: A64: Implement remaining integer scalar-3-same insns
Peter Maydell
2014-02-08
1
-19
/
+87
*
target-arm: A64: Implement scalar pairwise ops
Peter Maydell
2014-02-08
1
-1
/
+113
*
target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD
Peter Maydell
2014-02-08
1
-1
/
+123
*
target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns
Peter Maydell
2014-02-08
1
-4
/
+127
*
target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns
Peter Maydell
2014-02-08
1
-22
/
+112
*
target-arm: A64: Add SIMD shift by immediate
Alex Bennée
2014-01-31
1
-2
/
+373
*
target-arm: A64: Add simple SIMD 3-same floating point ops
Peter Maydell
2014-01-31
1
-2
/
+188
*
target-arm: A64: Add integer ops from SIMD 3-same group
Peter Maydell
2014-01-31
1
-1
/
+164
*
target-arm: A64: Add logic ops from SIMD 3 same group
Peter Maydell
2014-01-31
1
-1
/
+72
*
target-arm: A64: Add top level decode for SIMD 3-same group
Peter Maydell
2014-01-31
1
-1
/
+44
*
target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops
Peter Maydell
2014-01-31
1
-1
/
+130
*
target-arm: A64: Add SIMD three-different ABDL instructions
Peter Maydell
2014-01-31
1
-2
/
+33
*
target-arm: A64: Add SIMD three-different multiply accumulate insns
Peter Maydell
2014-01-31
1
-1
/
+232
*
target-arm: Move arm_rmode_to_sf to a shared location.
Will Newton
2014-01-31
1
-28
/
+0
*
target-arm: A64: Add SIMD scalar copy instructions
Peter Maydell
2014-01-31
1
-1
/
+42
*
target-arm: A64: Add SIMD modified immediate group
Alex Bennée
2014-01-31
1
-1
/
+119
*
target-arm: A64: Add SIMD copy operations
Alex Bennée
2014-01-31
1
-1
/
+209
*
target-arm: A64: Add SIMD across-lanes instructions
Michael Matz
2014-01-31
1
-1
/
+176
*
target-arm: A64: Add SIMD ZIP/UZP/TRN
Michael Matz
2014-01-31
1
-1
/
+75
*
target-arm: A64: Add SIMD TBL/TBLX
Michael Matz
2014-01-31
1
-1
/
+54
*
target-arm: A64: Add SIMD EXT
Peter Maydell
2014-01-31
1
-1
/
+78
*
target-arm: A64: Add decode skeleton for SIMD data processing insns
Alex Bennée
2014-01-31
1
-1
/
+305
*
target-arm: A64: Add SIMD ld/st single
Peter Maydell
2014-01-31
1
-2
/
+142
*
target-arm: A64: Add SIMD ld/st multiple
Alex Bennée
2014-01-31
1
-2
/
+248
*
target-arm: A64: Add support for FCVT between half, single and double
Peter Maydell
2014-01-08
1
-1
/
+74
*
target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions
Peter Maydell
2014-01-08
1
-1
/
+141
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