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path: root/target-arm/translate-a64.c
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* target-arm/translate-a64.c: Correct unallocated checks for ldst_exclPeter Maydell2015-11-241-13/+2
* target-arm: Update PC before calling gen_helper_check_breakpoints()Sergey Fedorov2015-11-121-0/+1
* target-arm: Report S/NS status in the CPU debug logsPeter Maydell2015-11-031-1/+10
* target-arm: Bring AArch64 debug CPU display of PSTATE into line with AArch32Peter Maydell2015-11-031-3/+5
* target-*: Advance pc after recognizing a breakpointRichard Henderson2015-10-281-2/+5
* target-arm: Fix CPU breakpoint handlingSergey Fedorov2015-10-161-5/+12
* target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin2015-10-161-1/+7
* tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-071-27/+3
* tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-071-0/+3
* target-arm: Add condexec state to insn_startRichard Henderson2015-10-071-1/+1
* target-*: Introduce and use cpu_breakpoint_testRichard Henderson2015-10-071-13/+13
* target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson2015-10-071-3/+3
* target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson2015-10-071-4/+1
* tcg: Rename debug_insn_start to insn_startRichard Henderson2015-10-071-1/+1
* target-arm: Use tcg_gen_extrh_i64_i32Richard Henderson2015-09-141-25/+9
* target-arm: Recognize RORRichard Henderson2015-09-141-12/+21
* target-arm: Eliminate unnecessary zero-extend in disas_bitfieldRichard Henderson2015-09-141-1/+5
* target-arm: Recognize UXTB, UXTH, LSR, LSLRichard Henderson2015-09-141-0/+17
* target-arm: Recognize SXTB, SXTH, SXTW, ASRRichard Henderson2015-09-141-1/+23
* target-arm: Implement fcsel with movcondRichard Henderson2015-09-141-28/+17
* target-arm: Implement ccmp branchlessRichard Henderson2015-09-141-16/+58
* target-arm: Use setcond and movcond for cselRichard Henderson2015-09-141-36/+49
* target-arm: Share all common TCG temporariesRichard Henderson2015-09-141-22/+0
* target-arm: Fix default_exception_el() function for the case when EL3 is not ...Sergey Sorokin2015-09-081-1/+5
* target-arm: Wire up HLT 0xf000 as the A64 semihosting instructionPeter Maydell2015-09-071-2/+22
* tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson2015-08-241-30/+30
* target-arm: Split DISAS_YIELD from DISAS_WFEPeter Maydell2015-07-061-0/+6
* disas: Remove uses of CPU envPeter Crosthwaite2015-06-221-1/+1
* target-arm: Don't halt on WFI unless we don't have any workPeter Maydell2015-05-291-0/+4
* target-arm: Extend FP checks to use an ELGreg Bellows2015-05-291-4/+4
* target-arm: Make singlestate TB flags common between AArch32/64Peter Maydell2015-05-291-2/+2
* target-arm: Add exception target el infrastructureGreg Bellows2015-05-291-12/+22
* tcg: Change translator-side labels to a pointerRichard Henderson2015-03-131-13/+13
* Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150212' into stagingPeter Maydell2015-02-131-7/+3
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| * tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-121-6/+3
| * tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson2015-02-121-1/+0
* | target-arm: A64: Avoid signed shifts in disas_ldst_pair()Peter Maydell2015-02-131-1/+1
* | target-arm: A64: Avoid left shifting negative integers in disas_pc_rel_addrPeter Maydell2015-02-131-2/+3
* | target-arm: A64: Fix handling of rotate in logic_imm_decode_wmaskPeter Maydell2015-02-131-1/+4
* | target-arm: A64: Fix shifts into sign bitPeter Maydell2015-02-131-3/+3
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* target-arm: Use correct mmu_idx for unprivileged loads and storesPeter Maydell2015-02-051-1/+18
* target-arm: Define correct mmu_idx values and pass them in TB flagsPeter Maydell2015-02-051-2/+3
* target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STTPeter Maydell2015-02-051-1/+1
* gen-icount: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-1/+1
* translate: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-2/+2
* target-arm: A64: remove redundant storeAlex Bennée2014-11-021-1/+0
* target-arm: rename arm_current_pl to arm_current_elGreg Bellows2014-10-241-8/+8
* target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpersPeter Maydell2014-10-241-2/+2
* target-arm: A64: Emulate the SMC insnEdgar E. Iglesias2014-09-291-0/+13
* target-arm: A64: Emulate the HVC insnEdgar E. Iglesias2014-09-291-9/+22
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