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path: root/target-arm/translate-a64.c
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* target-arm: A64: Implement MSR (immediate) instructionsPeter Maydell2014-02-261-1/+24
* target-arm: A64: Implement WFIPeter Maydell2014-02-261-1/+4
* target-arm: Get MMU index information correct for A64 codePeter Maydell2014-02-261-1/+1
* target-arm: Implement AArch64 CurrentEL sysregPeter Maydell2014-02-261-0/+7
* target-arm: A64: Implement unprivileged load/storePeter Maydell2014-02-201-32/+37
* target-arm: A64: Implement narrowing three-reg-diff operationsPeter Maydell2014-02-201-1/+59
* target-arm: A64: Implement the wide 3-reg-different operationsPeter Maydell2014-02-201-1/+40
* target-arm: A64: Add most remaining three-reg-diff widening opsPeter Maydell2014-02-201-21/+88
* target-arm: A64: Add opcode comments to disas_simd_three_reg_diffPeter Maydell2014-02-201-11/+11
* target-arm: A64: Implement store-exclusive for system modePeter Maydell2014-02-201-6/+62
* target-arm: Remove unnecessary code now read/write fns can't failPeter Maydell2014-02-201-2/+0
* target-arm: Split cpreg access checks out from read/write functionsPeter Maydell2014-02-201-0/+11
* target-arm: Log bad system register accesses with LOG_UNIMPPeter Maydell2014-02-201-1/+6
* target-arm: A64: Implement remaining 3-same instructionsPeter Maydell2014-02-201-4/+48
* target-arm: A64: Implement floating point pairwise insnsAlex Bennée2014-02-201-38/+86
* target-arm: A64: Implement SIMD FP compare and set insnsAlex Bennée2014-02-201-12/+185
* target-arm: A64: Implement scalar three different instructionsPeter Maydell2014-02-201-1/+94
* target-arm: A64: Implement SIMD scalar indexed instructionsPeter Maydell2014-02-201-33/+82
* target-arm: A64: Implement long vector x indexed insnsPeter Maydell2014-02-201-5/+139
* target-arm: A64: Implement plain vector SIMD indexed element insnsPeter Maydell2014-02-201-1/+247
* disas: Implement disassembly output for A64Claudio Fontana2014-02-081-1/+1
* target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc groupPeter Maydell2014-02-081-3/+20
* target-arm: A64: Add 2-reg-misc REV* instructionsAlex Bennée2014-02-081-1/+70
* target-arm: A64: Add narrowing 2-reg-misc instructionsPeter Maydell2014-02-081-2/+83
* target-arm: A64: Implement 2-reg-misc CNT, NOT and RBITPeter Maydell2014-02-081-6/+28
* target-arm: A64: Implement 2-register misc compares, ABS, NEGPeter Maydell2014-02-081-2/+134
* target-arm: A64: Add skeleton decode for SIMD 2-reg misc groupPeter Maydell2014-02-081-1/+109
* target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg miscPeter Maydell2014-02-081-1/+86
* target-arm: A64: Implement remaining integer scalar-3-same insnsPeter Maydell2014-02-081-19/+87
* target-arm: A64: Implement scalar pairwise opsPeter Maydell2014-02-081-1/+113
* target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMDPeter Maydell2014-02-081-1/+123
* target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insnsPeter Maydell2014-02-081-4/+127
* target-arm: A64: Implement SIMD 3-reg-same shift and saturate insnsPeter Maydell2014-02-081-22/+112
* target-arm: A64: Add SIMD shift by immediateAlex Bennée2014-01-311-2/+373
* target-arm: A64: Add simple SIMD 3-same floating point opsPeter Maydell2014-01-311-2/+188
* target-arm: A64: Add integer ops from SIMD 3-same groupPeter Maydell2014-01-311-1/+164
* target-arm: A64: Add logic ops from SIMD 3 same groupPeter Maydell2014-01-311-1/+72
* target-arm: A64: Add top level decode for SIMD 3-same groupPeter Maydell2014-01-311-1/+44
* target-arm: A64: Add SIMD scalar 3 same add, sub and compare opsPeter Maydell2014-01-311-1/+130
* target-arm: A64: Add SIMD three-different ABDL instructionsPeter Maydell2014-01-311-2/+33
* target-arm: A64: Add SIMD three-different multiply accumulate insnsPeter Maydell2014-01-311-1/+232
* target-arm: Move arm_rmode_to_sf to a shared location.Will Newton2014-01-311-28/+0
* target-arm: A64: Add SIMD scalar copy instructionsPeter Maydell2014-01-311-1/+42
* target-arm: A64: Add SIMD modified immediate groupAlex Bennée2014-01-311-1/+119
* target-arm: A64: Add SIMD copy operationsAlex Bennée2014-01-311-1/+209
* target-arm: A64: Add SIMD across-lanes instructionsMichael Matz2014-01-311-1/+176
* target-arm: A64: Add SIMD ZIP/UZP/TRNMichael Matz2014-01-311-1/+75
* target-arm: A64: Add SIMD TBL/TBLXMichael Matz2014-01-311-1/+54
* target-arm: A64: Add SIMD EXTPeter Maydell2014-01-311-1/+78
* target-arm: A64: Add decode skeleton for SIMD data processing insnsAlex Bennée2014-01-311-1/+305
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