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path: root/target-arm/translate-a64.c
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* disas: Implement disassembly output for A64Claudio Fontana2014-02-081-1/+1
* target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc groupPeter Maydell2014-02-081-3/+20
* target-arm: A64: Add 2-reg-misc REV* instructionsAlex Bennée2014-02-081-1/+70
* target-arm: A64: Add narrowing 2-reg-misc instructionsPeter Maydell2014-02-081-2/+83
* target-arm: A64: Implement 2-reg-misc CNT, NOT and RBITPeter Maydell2014-02-081-6/+28
* target-arm: A64: Implement 2-register misc compares, ABS, NEGPeter Maydell2014-02-081-2/+134
* target-arm: A64: Add skeleton decode for SIMD 2-reg misc groupPeter Maydell2014-02-081-1/+109
* target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg miscPeter Maydell2014-02-081-1/+86
* target-arm: A64: Implement remaining integer scalar-3-same insnsPeter Maydell2014-02-081-19/+87
* target-arm: A64: Implement scalar pairwise opsPeter Maydell2014-02-081-1/+113
* target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMDPeter Maydell2014-02-081-1/+123
* target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insnsPeter Maydell2014-02-081-4/+127
* target-arm: A64: Implement SIMD 3-reg-same shift and saturate insnsPeter Maydell2014-02-081-22/+112
* target-arm: A64: Add SIMD shift by immediateAlex Bennée2014-01-311-2/+373
* target-arm: A64: Add simple SIMD 3-same floating point opsPeter Maydell2014-01-311-2/+188
* target-arm: A64: Add integer ops from SIMD 3-same groupPeter Maydell2014-01-311-1/+164
* target-arm: A64: Add logic ops from SIMD 3 same groupPeter Maydell2014-01-311-1/+72
* target-arm: A64: Add top level decode for SIMD 3-same groupPeter Maydell2014-01-311-1/+44
* target-arm: A64: Add SIMD scalar 3 same add, sub and compare opsPeter Maydell2014-01-311-1/+130
* target-arm: A64: Add SIMD three-different ABDL instructionsPeter Maydell2014-01-311-2/+33
* target-arm: A64: Add SIMD three-different multiply accumulate insnsPeter Maydell2014-01-311-1/+232
* target-arm: Move arm_rmode_to_sf to a shared location.Will Newton2014-01-311-28/+0
* target-arm: A64: Add SIMD scalar copy instructionsPeter Maydell2014-01-311-1/+42
* target-arm: A64: Add SIMD modified immediate groupAlex Bennée2014-01-311-1/+119
* target-arm: A64: Add SIMD copy operationsAlex Bennée2014-01-311-1/+209
* target-arm: A64: Add SIMD across-lanes instructionsMichael Matz2014-01-311-1/+176
* target-arm: A64: Add SIMD ZIP/UZP/TRNMichael Matz2014-01-311-1/+75
* target-arm: A64: Add SIMD TBL/TBLXMichael Matz2014-01-311-1/+54
* target-arm: A64: Add SIMD EXTPeter Maydell2014-01-311-1/+78
* target-arm: A64: Add decode skeleton for SIMD data processing insnsAlex Bennée2014-01-311-1/+305
* target-arm: A64: Add SIMD ld/st singlePeter Maydell2014-01-311-2/+142
* target-arm: A64: Add SIMD ld/st multipleAlex Bennée2014-01-311-2/+248
* target-arm: A64: Add support for FCVT between half, single and doublePeter Maydell2014-01-081-1/+74
* target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructionsPeter Maydell2014-01-081-1/+141
* target-arm: A64: Add floating-point<->integer conversion instructionsWill Newton2014-01-081-3/+20
* target-arm: A64: Add floating-point<->fixed-point instructionsAlexander Graf2014-01-081-1/+185
* target-arm: A64: Add support for floating point cond selectClaudio Fontana2014-01-081-1/+44
* target-arm: A64: Add support for floating point conditional compareClaudio Fontana2014-01-081-1/+34
* target-arm: A64: Add support for floating point compareClaudio Fontana2014-01-081-1/+64
* target-arm: A64: Add fmov (scalar, immediate) instructionAlexander Graf2014-01-081-1/+31
* target-arm: A64: Add "Floating-point data-processing (3 source)" insnsAlexander Graf2014-01-081-1/+94
* target-arm: A64: Add "Floating-point data-processing (2 source)" insnsAlexander Graf2014-01-081-1/+181
* target-arm: A64: Fix vector register access on bigendian hostsPeter Maydell2014-01-081-34/+35
* target-arm: A64: Add support for dumping AArch64 VFP register stateAlexander Graf2014-01-081-0/+16
* target-arm: A64: support for ld/st/cl exclusiveMichael Matz2014-01-081-3/+153
* target-arm: aarch64: add support for ld litAlexander Graf2014-01-081-2/+45
* target-arm: A64: add support for conditional compare insnsClaudio Fontana2014-01-081-13/+60
* target-arm: A64: add support for add/sub with carryClaudio Fontana2014-01-081-2/+103
* target-arm: A64: Implement minimal set of EL0-visible sysregsPeter Maydell2014-01-071-0/+52
* target-arm: A64: Implement MRS/MSR/SYS/SYSLPeter Maydell2014-01-071-30/+82
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