index
:
hqemu
2.5.1_overlay
2.5_overlay
2.6_overlay
master
HQEMU
Raptor Engineering, LLC
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
target-arm
/
translate-a64.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
disas: Implement disassembly output for A64
Claudio Fontana
2014-02-08
1
-1
/
+1
*
target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group
Peter Maydell
2014-02-08
1
-3
/
+20
*
target-arm: A64: Add 2-reg-misc REV* instructions
Alex Bennée
2014-02-08
1
-1
/
+70
*
target-arm: A64: Add narrowing 2-reg-misc instructions
Peter Maydell
2014-02-08
1
-2
/
+83
*
target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT
Peter Maydell
2014-02-08
1
-6
/
+28
*
target-arm: A64: Implement 2-register misc compares, ABS, NEG
Peter Maydell
2014-02-08
1
-2
/
+134
*
target-arm: A64: Add skeleton decode for SIMD 2-reg misc group
Peter Maydell
2014-02-08
1
-1
/
+109
*
target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc
Peter Maydell
2014-02-08
1
-1
/
+86
*
target-arm: A64: Implement remaining integer scalar-3-same insns
Peter Maydell
2014-02-08
1
-19
/
+87
*
target-arm: A64: Implement scalar pairwise ops
Peter Maydell
2014-02-08
1
-1
/
+113
*
target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD
Peter Maydell
2014-02-08
1
-1
/
+123
*
target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns
Peter Maydell
2014-02-08
1
-4
/
+127
*
target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns
Peter Maydell
2014-02-08
1
-22
/
+112
*
target-arm: A64: Add SIMD shift by immediate
Alex Bennée
2014-01-31
1
-2
/
+373
*
target-arm: A64: Add simple SIMD 3-same floating point ops
Peter Maydell
2014-01-31
1
-2
/
+188
*
target-arm: A64: Add integer ops from SIMD 3-same group
Peter Maydell
2014-01-31
1
-1
/
+164
*
target-arm: A64: Add logic ops from SIMD 3 same group
Peter Maydell
2014-01-31
1
-1
/
+72
*
target-arm: A64: Add top level decode for SIMD 3-same group
Peter Maydell
2014-01-31
1
-1
/
+44
*
target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops
Peter Maydell
2014-01-31
1
-1
/
+130
*
target-arm: A64: Add SIMD three-different ABDL instructions
Peter Maydell
2014-01-31
1
-2
/
+33
*
target-arm: A64: Add SIMD three-different multiply accumulate insns
Peter Maydell
2014-01-31
1
-1
/
+232
*
target-arm: Move arm_rmode_to_sf to a shared location.
Will Newton
2014-01-31
1
-28
/
+0
*
target-arm: A64: Add SIMD scalar copy instructions
Peter Maydell
2014-01-31
1
-1
/
+42
*
target-arm: A64: Add SIMD modified immediate group
Alex Bennée
2014-01-31
1
-1
/
+119
*
target-arm: A64: Add SIMD copy operations
Alex Bennée
2014-01-31
1
-1
/
+209
*
target-arm: A64: Add SIMD across-lanes instructions
Michael Matz
2014-01-31
1
-1
/
+176
*
target-arm: A64: Add SIMD ZIP/UZP/TRN
Michael Matz
2014-01-31
1
-1
/
+75
*
target-arm: A64: Add SIMD TBL/TBLX
Michael Matz
2014-01-31
1
-1
/
+54
*
target-arm: A64: Add SIMD EXT
Peter Maydell
2014-01-31
1
-1
/
+78
*
target-arm: A64: Add decode skeleton for SIMD data processing insns
Alex Bennée
2014-01-31
1
-1
/
+305
*
target-arm: A64: Add SIMD ld/st single
Peter Maydell
2014-01-31
1
-2
/
+142
*
target-arm: A64: Add SIMD ld/st multiple
Alex Bennée
2014-01-31
1
-2
/
+248
*
target-arm: A64: Add support for FCVT between half, single and double
Peter Maydell
2014-01-08
1
-1
/
+74
*
target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions
Peter Maydell
2014-01-08
1
-1
/
+141
*
target-arm: A64: Add floating-point<->integer conversion instructions
Will Newton
2014-01-08
1
-3
/
+20
*
target-arm: A64: Add floating-point<->fixed-point instructions
Alexander Graf
2014-01-08
1
-1
/
+185
*
target-arm: A64: Add support for floating point cond select
Claudio Fontana
2014-01-08
1
-1
/
+44
*
target-arm: A64: Add support for floating point conditional compare
Claudio Fontana
2014-01-08
1
-1
/
+34
*
target-arm: A64: Add support for floating point compare
Claudio Fontana
2014-01-08
1
-1
/
+64
*
target-arm: A64: Add fmov (scalar, immediate) instruction
Alexander Graf
2014-01-08
1
-1
/
+31
*
target-arm: A64: Add "Floating-point data-processing (3 source)" insns
Alexander Graf
2014-01-08
1
-1
/
+94
*
target-arm: A64: Add "Floating-point data-processing (2 source)" insns
Alexander Graf
2014-01-08
1
-1
/
+181
*
target-arm: A64: Fix vector register access on bigendian hosts
Peter Maydell
2014-01-08
1
-34
/
+35
*
target-arm: A64: Add support for dumping AArch64 VFP register state
Alexander Graf
2014-01-08
1
-0
/
+16
*
target-arm: A64: support for ld/st/cl exclusive
Michael Matz
2014-01-08
1
-3
/
+153
*
target-arm: aarch64: add support for ld lit
Alexander Graf
2014-01-08
1
-2
/
+45
*
target-arm: A64: add support for conditional compare insns
Claudio Fontana
2014-01-08
1
-13
/
+60
*
target-arm: A64: add support for add/sub with carry
Claudio Fontana
2014-01-08
1
-2
/
+103
*
target-arm: A64: Implement minimal set of EL0-visible sysregs
Peter Maydell
2014-01-07
1
-0
/
+52
*
target-arm: A64: Implement MRS/MSR/SYS/SYSL
Peter Maydell
2014-01-07
1
-30
/
+82
[next]