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target-arm
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translate-a64.c
Commit message (
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)
Author
Age
Files
Lines
*
target-arm: A64: Add support for FCVT between half, single and double
Peter Maydell
2014-01-08
1
-1
/
+74
*
target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions
Peter Maydell
2014-01-08
1
-1
/
+141
*
target-arm: A64: Add floating-point<->integer conversion instructions
Will Newton
2014-01-08
1
-3
/
+20
*
target-arm: A64: Add floating-point<->fixed-point instructions
Alexander Graf
2014-01-08
1
-1
/
+185
*
target-arm: A64: Add support for floating point cond select
Claudio Fontana
2014-01-08
1
-1
/
+44
*
target-arm: A64: Add support for floating point conditional compare
Claudio Fontana
2014-01-08
1
-1
/
+34
*
target-arm: A64: Add support for floating point compare
Claudio Fontana
2014-01-08
1
-1
/
+64
*
target-arm: A64: Add fmov (scalar, immediate) instruction
Alexander Graf
2014-01-08
1
-1
/
+31
*
target-arm: A64: Add "Floating-point data-processing (3 source)" insns
Alexander Graf
2014-01-08
1
-1
/
+94
*
target-arm: A64: Add "Floating-point data-processing (2 source)" insns
Alexander Graf
2014-01-08
1
-1
/
+181
*
target-arm: A64: Fix vector register access on bigendian hosts
Peter Maydell
2014-01-08
1
-34
/
+35
*
target-arm: A64: Add support for dumping AArch64 VFP register state
Alexander Graf
2014-01-08
1
-0
/
+16
*
target-arm: A64: support for ld/st/cl exclusive
Michael Matz
2014-01-08
1
-3
/
+153
*
target-arm: aarch64: add support for ld lit
Alexander Graf
2014-01-08
1
-2
/
+45
*
target-arm: A64: add support for conditional compare insns
Claudio Fontana
2014-01-08
1
-13
/
+60
*
target-arm: A64: add support for add/sub with carry
Claudio Fontana
2014-01-08
1
-2
/
+103
*
target-arm: A64: Implement minimal set of EL0-visible sysregs
Peter Maydell
2014-01-07
1
-0
/
+52
*
target-arm: A64: Implement MRS/MSR/SYS/SYSL
Peter Maydell
2014-01-07
1
-30
/
+82
*
target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder
Peter Maydell
2014-01-07
1
-0
/
+2
*
target-arm: A64: implement FMOV
Peter Maydell
2013-12-23
1
-1
/
+85
*
target-arm: A64: Add decoder skeleton for FP instructions
Peter Maydell
2013-12-23
1
-1
/
+169
*
target-arm: A64: implement SVC, BRK
Alexander Graf
2013-12-23
1
-2
/
+49
*
target-arm: A64: add support for 3 src data proc insns
Alexander Graf
2013-12-23
1
-2
/
+95
*
target-arm: A64: add support for move wide instructions
Alex Bennée
2013-12-23
1
-2
/
+49
*
target-arm: A64: add support for add, addi, sub, subi
Alex Bennée
2013-12-23
1
-6
/
+286
*
target-arm: A64: add support for ld/st with index
Alex Bennée
2013-12-23
1
-1
/
+124
*
target-arm: A64: add support for ld/st with reg offset
Alex Bennée
2013-12-23
1
-1
/
+143
*
target-arm: A64: add support for ld/st unsigned imm
Alex Bennée
2013-12-23
1
-1
/
+88
*
target-arm: A64: add support for ld/st pair
Peter Maydell
2013-12-23
1
-2
/
+277
*
target-arm: A64: add support for logical (immediate) insns
Alexander Graf
2013-12-17
1
-2
/
+173
*
target-arm: A64: add support for 1-src CLS insn
Claudio Fontana
2013-12-17
1
-1
/
+19
*
target-arm: A64: add support for bitfield insns
Claudio Fontana
2013-12-17
1
-2
/
+54
*
target-arm: A64: add support for 1-src REV insns
Claudio Fontana
2013-12-17
1
-1
/
+72
*
target-arm: A64: add support for 1-src RBIT insn
Alexander Graf
2013-12-17
1
-0
/
+20
*
target-arm: A64: add support for 1-src data processing and CLZ
Claudio Fontana
2013-12-17
1
-2
/
+50
*
target-arm: A64: add support for 2-src shift reg insns
Alexander Graf
2013-12-17
1
-0
/
+22
*
target-arm: A64: add support for 2-src data processing and DIV
Alexander Graf
2013-12-17
1
-2
/
+70
*
target-arm: A64: add support for EXTR
Alexander Graf
2013-12-17
1
-2
/
+47
*
target-arm: A64: add support for ADR and ADRP
Alexander Graf
2013-12-17
1
-2
/
+23
*
target-arm: A64: add support for logical (shifted register)
Alexander Graf
2013-12-17
1
-6
/
+191
*
target-arm: A64: add support for conditional select
Claudio Fontana
2013-12-17
1
-2
/
+65
*
target-arm: A64: add support for compare and branch imm
Alexander Graf
2013-12-17
1
-2
/
+44
*
target-arm: A64: add support for 'test and branch' imm
Alexander Graf
2013-12-17
1
-2
/
+25
*
target-arm: A64: add support for conditional branches
Alexander Graf
2013-12-17
1
-2
/
+27
*
target-arm: A64: add support for BR, BLR and RET insns
Alexander Graf
2013-12-17
1
-2
/
+41
*
target-arm: A64: add support for B and BL insns
Alexander Graf
2013-12-17
1
-2
/
+62
*
target-arm: A64: expand decoding skeleton for system instructions
Claudio Fontana
2013-12-17
1
-2
/
+129
*
target-arm: A64: provide skeleton for a64 insn decoding
Claudio Fontana
2013-12-17
1
-8
/
+362
*
target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()
Peter Maydell
2013-12-17
1
-5
/
+204
*
target-arm: Clean up handling of AArch64 PSTATE
Peter Maydell
2013-12-17
1
-5
/
+7
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