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path: root/target-arm/translate-a64.c
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* target-arm: A64: Add support for FCVT between half, single and doublePeter Maydell2014-01-081-1/+74
* target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructionsPeter Maydell2014-01-081-1/+141
* target-arm: A64: Add floating-point<->integer conversion instructionsWill Newton2014-01-081-3/+20
* target-arm: A64: Add floating-point<->fixed-point instructionsAlexander Graf2014-01-081-1/+185
* target-arm: A64: Add support for floating point cond selectClaudio Fontana2014-01-081-1/+44
* target-arm: A64: Add support for floating point conditional compareClaudio Fontana2014-01-081-1/+34
* target-arm: A64: Add support for floating point compareClaudio Fontana2014-01-081-1/+64
* target-arm: A64: Add fmov (scalar, immediate) instructionAlexander Graf2014-01-081-1/+31
* target-arm: A64: Add "Floating-point data-processing (3 source)" insnsAlexander Graf2014-01-081-1/+94
* target-arm: A64: Add "Floating-point data-processing (2 source)" insnsAlexander Graf2014-01-081-1/+181
* target-arm: A64: Fix vector register access on bigendian hostsPeter Maydell2014-01-081-34/+35
* target-arm: A64: Add support for dumping AArch64 VFP register stateAlexander Graf2014-01-081-0/+16
* target-arm: A64: support for ld/st/cl exclusiveMichael Matz2014-01-081-3/+153
* target-arm: aarch64: add support for ld litAlexander Graf2014-01-081-2/+45
* target-arm: A64: add support for conditional compare insnsClaudio Fontana2014-01-081-13/+60
* target-arm: A64: add support for add/sub with carryClaudio Fontana2014-01-081-2/+103
* target-arm: A64: Implement minimal set of EL0-visible sysregsPeter Maydell2014-01-071-0/+52
* target-arm: A64: Implement MRS/MSR/SYS/SYSLPeter Maydell2014-01-071-30/+82
* target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoderPeter Maydell2014-01-071-0/+2
* target-arm: A64: implement FMOVPeter Maydell2013-12-231-1/+85
* target-arm: A64: Add decoder skeleton for FP instructionsPeter Maydell2013-12-231-1/+169
* target-arm: A64: implement SVC, BRKAlexander Graf2013-12-231-2/+49
* target-arm: A64: add support for 3 src data proc insnsAlexander Graf2013-12-231-2/+95
* target-arm: A64: add support for move wide instructionsAlex Bennée2013-12-231-2/+49
* target-arm: A64: add support for add, addi, sub, subiAlex Bennée2013-12-231-6/+286
* target-arm: A64: add support for ld/st with indexAlex Bennée2013-12-231-1/+124
* target-arm: A64: add support for ld/st with reg offsetAlex Bennée2013-12-231-1/+143
* target-arm: A64: add support for ld/st unsigned immAlex Bennée2013-12-231-1/+88
* target-arm: A64: add support for ld/st pairPeter Maydell2013-12-231-2/+277
* target-arm: A64: add support for logical (immediate) insnsAlexander Graf2013-12-171-2/+173
* target-arm: A64: add support for 1-src CLS insnClaudio Fontana2013-12-171-1/+19
* target-arm: A64: add support for bitfield insnsClaudio Fontana2013-12-171-2/+54
* target-arm: A64: add support for 1-src REV insnsClaudio Fontana2013-12-171-1/+72
* target-arm: A64: add support for 1-src RBIT insnAlexander Graf2013-12-171-0/+20
* target-arm: A64: add support for 1-src data processing and CLZClaudio Fontana2013-12-171-2/+50
* target-arm: A64: add support for 2-src shift reg insnsAlexander Graf2013-12-171-0/+22
* target-arm: A64: add support for 2-src data processing and DIVAlexander Graf2013-12-171-2/+70
* target-arm: A64: add support for EXTRAlexander Graf2013-12-171-2/+47
* target-arm: A64: add support for ADR and ADRPAlexander Graf2013-12-171-2/+23
* target-arm: A64: add support for logical (shifted register)Alexander Graf2013-12-171-6/+191
* target-arm: A64: add support for conditional selectClaudio Fontana2013-12-171-2/+65
* target-arm: A64: add support for compare and branch immAlexander Graf2013-12-171-2/+44
* target-arm: A64: add support for 'test and branch' immAlexander Graf2013-12-171-2/+25
* target-arm: A64: add support for conditional branchesAlexander Graf2013-12-171-2/+27
* target-arm: A64: add support for BR, BLR and RET insnsAlexander Graf2013-12-171-2/+41
* target-arm: A64: add support for B and BL insnsAlexander Graf2013-12-171-2/+62
* target-arm: A64: expand decoding skeleton for system instructionsClaudio Fontana2013-12-171-2/+129
* target-arm: A64: provide skeleton for a64 insn decodingClaudio Fontana2013-12-171-8/+362
* target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()Peter Maydell2013-12-171-5/+204
* target-arm: Clean up handling of AArch64 PSTATEPeter Maydell2013-12-171-5/+7
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