summaryrefslogtreecommitdiffstats
path: root/target-arm/helper.c
Commit message (Expand)AuthorAgeFilesLines
* target-arm: implement SCTLR.B, drop bswap_codePaolo Bonzini2019-11-291-4/+4
* target-arm: Correct handling of writes to CPSR mode bits from gdb in usermodePeter Maydell2019-11-291-2/+9
* target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEFPeter Maydell2019-11-291-7/+121
* target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAWEdgar E. Iglesias2019-11-291-1/+1
* target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM trapsPeter Maydell2019-11-291-7/+36
* target-arm: Fix handling of SDCR for 32-bit codePeter Maydell2019-11-291-8/+15
* target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1Peter Maydell2019-11-291-0/+10
* target-arm: Make mode switches from Hyp via CPS and MRS illegalPeter Maydell2019-11-291-2/+10
* target-arm: In v8, make illegal AArch32 mode changes set PSTATE.ILPeter Maydell2019-11-291-3/+12
* target-arm: Forbid mode switch to Mon from Secure EL1Peter Maydell2019-11-291-1/+1
* target-arm: Add Hyp mode checks to bad_mode_switch()Peter Maydell2019-11-291-0/+3
* target-arm: Add comment about not implementing NSACR.RFRPeter Maydell2019-11-291-0/+3
* target-arm: In cpsr_write() ignore mode switches from User modePeter Maydell2019-11-291-0/+1
* target-arm: Raw CPSR writes should skip checks and bank switchingPeter Maydell2019-11-291-2/+3
* target-arm: Add write_type argument to cpsr_write()Peter Maydell2019-11-291-1/+2
* target-arm: Add PMUSERENR_EL0 registerAlistair Francis2019-11-291-0/+6
* target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registersAlistair Francis2019-11-291-0/+12
* target-arm: Add the pmceid0 and pmceid1 registersAlistair Francis2019-11-291-0/+16
* target-arm: Move bank_number() into internals.hPeter Maydell2019-11-291-25/+0
* target-arm: Move get/set_r13_banked() to op_helper.cPeter Maydell2019-11-291-33/+0
* target-arm: Report correct syndrome for FPEXC32_EL2 trapsPeter Maydell2019-11-291-2/+2
* target-arm: Implement MDCR_EL3.TDA and MDCR_EL2.TDA trapsPeter Maydell2019-11-291-9/+30
* target-arm: Implement MDCR_EL2.TDRA trapsPeter Maydell2019-11-291-3/+24
* target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA trapsPeter Maydell2019-11-291-1/+22
* target-arm: correct CNTFRQ access rightsPeter Maydell2019-11-291-3/+26
* target-arm: Implement NSACR trapping behaviourPeter Maydell2019-11-291-4/+58
* target-arm: Add isread parameter to CPAccessFnsPeter Maydell2019-11-291-29/+52
* target-arm: Use access_trap_aa32s_el1() for SCR and MVBARPeter Maydell2019-11-291-2/+4
* target-arm: Implement MDCR_EL3 and SDCRPeter Maydell2019-11-291-0/+26
* target-arm: Implement the S2 MMU inputsize > pamax checkEdgar E. Iglesias2019-11-291-0/+8
* target-arm: Rename check_s2_startlevel to check_s2_mmu_setupEdgar E. Iglesias2019-11-291-6/+6
* target-arm: Apply S2 MMU startlevel table size check to AArch64Edgar E. Iglesias2019-11-291-8/+8
* target-arm: Make various system registers visible to EL3Peter Maydell2019-11-291-29/+29
* target-arm: Implement FPEXC32_EL2 system registerPeter Maydell2019-11-291-0/+16
* target-arm: Fix wrong AArch64 entry offset for EL2/EL3 targetPeter Maydell2019-11-291-1/+20
* target-arm: Pull semihosting handling out to arm_cpu_do_interrupt()Peter Maydell2019-11-291-39/+81
* target-arm: Use a single entry point for AArch64 and AArch32 exceptionsPeter Maydell2019-11-291-31/+44
* target-arm: Move aarch64_cpu_do_interrupt() to helper.cPeter Maydell2019-11-291-0/+100
* target-arm: Support multiple address spaces in page table walksPeter Maydell2019-11-291-2/+6
* target-arm: Implement cpu_get_phys_page_attrs_debugPeter Maydell2019-11-291-4/+5
* target-arm: Clean up includesPeter Maydell2019-11-291-0/+1
* target-arm: Use the right MMU index in arm_regime_using_lpae_formatAlvise Rigo2019-11-291-4/+8
* target-arm: raise exception on misaligned LDREX operandsAndrew Baumann2019-11-291-0/+8
* Initial overlay of HQEMU 2.5.2 changes onto underlying 2.5.0 QEMU GIT tree2.5_overlayTimothy Pearson2019-11-291-20/+26
* target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8Peter Maydell2015-11-241-1/+11
* target-arm: Add and use symbolic names for register banksSoren Brinkmann2015-11-031-15/+22
* target-arm: Add support for S1 + S2 MMU translationsEdgar E. Iglesias2015-10-271-7/+31
* target-arm: Add S2 translation to 32bit S1 PTWsEdgar E. Iglesias2015-10-271-5/+17
* target-arm: Add S2 translation to 64bit S1 PTWsEdgar E. Iglesias2015-10-271-2/+48
* target-arm: Add ARMMMUFaultInfoEdgar E. Iglesias2015-10-271-12/+20
OpenPOWER on IntegriCloud