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path: root/target-arm/helper.c
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* target-arm: Add 32/64-bit register syncGreg Bellows2015-02-131-0/+211
* target-arm: fix for exponent comparison in recpe_f64Ildar Isaev2015-02-051-1/+1
* target-arm: Fix brace style in reindented codePeter Maydell2015-02-051-13/+23
* target-arm: Reindent ancient page-table-walk codePeter Maydell2015-02-051-96/+96
* target-arm: Use mmu_idx in get_phys_addr()Peter Maydell2015-02-051-51/+163
* target-arm: Pass mmu_idx to get_phys_addr()Peter Maydell2015-02-051-14/+96
* target-arm: Split AArch64 cases out of ats_write()Peter Maydell2015-02-051-7/+26
* target-arm: Define correct mmu_idx values and pass them in TB flagsPeter Maydell2015-02-051-1/+2
* target-arm: Add checks that cpreg raw accesses are handledPeter Maydell2015-02-051-0/+31
* target-arm: Split NO_MIGRATE into ALIAS and NO_RAWPeter Maydell2015-02-051-104/+106
* target-arm: Add missing SP_ELx register definitionGreg Bellows2015-02-051-0/+8
* target-arm: Add extended RVBAR supportGreg Bellows2015-02-051-6/+25
* target-arm: Fix RVBAR_EL1 register encodingGreg Bellows2015-02-051-1/+1
* target-arm: Fix typo in comment (seperately -> separately)Stefan Weil2015-01-151-1/+1
* target-arm: Merge EL3 CP15 register listsGreg Bellows2014-12-221-31/+24
* target-arm: make MAIR0/1 bankedGreg Bellows2014-12-111-3/+9
* target-arm: make c13 cp regs banked (FCSEIDR, ...)Fabian Aggeler2014-12-111-13/+45
* target-arm: make VBAR bankedGreg Bellows2014-12-111-2/+3
* target-arm: make PAR bankedFabian Aggeler2014-12-111-10/+13
* target-arm: make IFAR/DFAR bankedFabian Aggeler2014-12-111-7/+9
* target-arm: make DFSR bankedFabian Aggeler2014-12-111-3/+4
* target-arm: make IFSR bankedFabian Aggeler2014-12-111-4/+9
* target-arm: make DACR bankedFabian Aggeler2014-12-111-10/+18
* target-arm: make TTBCR bankedFabian Aggeler2014-12-111-25/+47
* target-arm: make TTBR0/1 bankedFabian Aggeler2014-12-111-12/+25
* target-arm: make CSSELR bankedFabian Aggeler2014-12-111-3/+11
* target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFIFabian Aggeler2014-12-111-0/+54
* target-arm: add SCTLR_EL3 and make SCTLR bankedFabian Aggeler2014-12-111-30/+42
* target-arm: add MVBAR supportFabian Aggeler2014-12-111-6/+9
* target-arm: add SDER definitionGreg Bellows2014-12-111-0/+8
* target-arm: add NSACR registerFabian Aggeler2014-12-111-0/+4
* target-arm: implement IRQ/FIQ routing to Monitor modeFabian Aggeler2014-12-111-0/+9
* target-arm: move AArch32 SCR into security reglistFabian Aggeler2014-12-111-6/+13
* target-arm: insert AArch32 cpregs twice into hashtableFabian Aggeler2014-12-111-17/+81
* target-arm: add secure state bit to CPREG hashPeter Maydell2014-12-111-3/+4
* target-arm: add async excp target_el functionGreg Bellows2014-12-111-19/+97
* target-arm: handle address translations that start at level 3Peter Maydell2014-11-171-9/+11
* target-arm: A32: Emulate the SMC instructionFabian Aggeler2014-10-241-0/+11
* target-arm: rename arm_current_pl to arm_current_elGreg Bellows2014-10-241-11/+11
* target-arm: reject switching to monitor modeSergey Fedorov2014-10-241-0/+2
* target-arm: Correct sense of the DCZID DZP bitPeter Maydell2014-10-241-1/+1
* target-arm: add emulation of PSCI calls for system emulationRob Herring2014-10-241-0/+6
* target-arm: do not set do_interrupt handlers for ARM and AArch64 user modesRob Herring2014-10-241-5/+0
* target-arm: Add support for VIRQ and VFIQEdgar E. Iglesias2014-09-291-0/+4
* target-arm: Add IRQ and FIQ routing to EL2 and 3Edgar E. Iglesias2014-09-291-0/+17
* target-arm: A64: Emulate the SMC insnEdgar E. Iglesias2014-09-291-0/+3
* target-arm: Add a Hypervisor Trap exception typeEdgar E. Iglesias2014-09-291-0/+1
* target-arm: A64: Emulate the HVC insnEdgar E. Iglesias2014-09-291-1/+19
* target-arm: A64: Refactor aarch64_cpu_do_interruptEdgar E. Iglesias2014-09-291-0/+13
* target-arm: Add SCR_EL3Edgar E. Iglesias2014-09-291-2/+33
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