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* target-arm: Implement setting guest breakpointsPeter Maydell2014-09-291-2/+124
| | | | | | | | | | This patch adds support for setting guest breakpoints based on values the guest writes to the DBGBVR and DBGBCR registers. (It doesn't include the code to handle when these breakpoints fire, so has no guest-visible effect.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1410523465-13400-2-git-send-email-peter.maydell@linaro.org
* target-arm: Make *IS TLB maintenance ops affect all CPUsPeter Maydell2014-09-121-12/+89
| | | | | | | | | | | | The ARM architecture defines that the "IS" variants of TLB maintenance operations must affect all TLBs in the Inner Shareable domain, which for us means all CPUs. We were incorrectly implementing these to only affect the current CPU, which meant that SMP TCG operation was unstable. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1410274883-9578-3-git-send-email-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org
* target-arm: Push legacy wildcard TLB ops back into v6Peter Maydell2014-09-121-47/+55
| | | | | | | | | | | | | | | | | | | | When we implemented ARMv8 in QEMU we retained our legacy loose wildcarded decoding of the TLB maintenance operations for v7 and earlier CPUs and provided the correct stricter decode for v8. However the loose decode is in fact wrong for v7MP, because it doesn't correctly implement the operations which must apply to every CPU in the Inner Shareable domain. Move the legacy wildcarding from the not_v8 reginfo array into the not_v7 array, and move the strictly decoded operations from the v8 reginfo to v7 or v7mp arrays as appropriate. Cache and TLB lockdown legacy wildcarding remains in the not_v8 array for the moment. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1410274883-9578-2-git-send-email-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org
* target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0Peter Maydell2014-09-121-0/+19
| | | | | | | | | Implement debug registers DBGVCR, OSDLR_EL1 and MDCCSR_EL0 (as dummy or limited-functionality). 32 bit Linux kernels will access these at startup so they are required for breakpoints and watchpoints to be supported. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Remove comment about MDSCR_EL1 being dummy implementationPeter Maydell2014-09-121-3/+1
| | | | | | | MDSCR_EL1 has actual functionality now; remove the out of date comment that claims it is a dummy implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32Peter Maydell2014-09-121-0/+26
| | | | | | | | | For debug exceptions taken to AArch32 we have to set the DBGDSCR.MOE (Method Of Entry) bits; we can identify the kind of debug exception from the information in exception.syndrome. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement handling of fired watchpointsPeter Maydell2014-09-121-1/+6
| | | | | | | Implement the ARM debug exception handler for dealing with fired watchpoints. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Move extended_addresses_enabled() to internals.hPeter Maydell2014-09-121-11/+0
| | | | | | | Move the utility function extended_addresses_enabled() into internals.h; we're going to need to call it from op_helper.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement setting of watchpointsPeter Maydell2014-09-121-3/+132
| | | | | | | | | Implement support for setting QEMU watchpoints based on the values the guest writes to the ARM architected watchpoint registers. (We do not yet report the firing of the watchpoints to the guest, so they will just be ignored.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement pmccfiltr_write functionAlistair Francis2014-08-291-0/+9
| | | | | | | | | | This is the function that is called when writing to the PMCCFILTR_EL0 register Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 73da3da6404855b17d5ae82975a32ff3a4dcae3d.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Remove old code and replace with new functionsAlistair Francis2014-08-291-23/+4
| | | | | | | | | | Remove the old PMCCNTR code and replace it with calls to the new pmccntr_sync() and arm_ccnt_enabled() functions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 693a6e437d915c2195fd3dc7303f384ca538b7bf.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement pmccntr_sync functionAlistair Francis2014-08-291-0/+23
| | | | | | | | | | | | | This is used to synchronise the PMCCNTR counter and swap its state between enabled and disabled if required. It must always be called twice, both before and after any logic that could change the state of the PMCCNTR counter. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 62811d4c0f7b1384f7aab62ea2fcfda3dcb0db50.1409025949.git.peter.crosthwaite@xilinx.com [PMM: fixed minor typos in pmccntr_sync doc comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add arm_ccnt_enabled functionAlistair Francis2014-08-291-0/+12
| | | | | | | | | | | | | | Include a helper function to determine if the CCNT counter is enabled. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: e1a64f17a756e06c8bda8238ad4826d705049f7a.1409025949.git.peter.crosthwaite@xilinx.com [ PC changes * Remove EL based checks ] Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement PMCCNTR_EL0 and related registersAlistair Francis2014-08-291-6/+39
| | | | | | | | | | | This patch adds support for the ARMv8 version of the PMCCNTR and related registers. It also starts to implement the PMCCFILTR_EL0 register. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: b5d1094764a5416363ee95216799b394ecd011e8.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: Implement PMCCNTR 32b read-modify-writePeter Crosthwaite2014-08-291-1/+10
| | | | | | | | | | | The register is now 64bit, however a 32 bit write to the register should leave the higher bits unchanged. The open coded write handler does not implement this, so we need to read-modify-write accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Alistair Francis <alistair23@gmail.com> Message-id: ec350573424bb2adc1701c3b9278d26598e2f2d1.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Make the ARM PMCCNTR register 64-bitAlistair Francis2014-08-291-10/+9
| | | | | | | | | | This makes the PMCCNTR register 64-bit to allow for the 64-bit ARMv8 version. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 6c5bac5fd0ea54963b1fc0e7f9464909f2e19a73.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement MDSCR_EL1 as having statePeter Maydell2014-08-191-1/+3
| | | | | | | | | Now that all the new code to support single-stepping is in place, wire up the guest-visible MDSCR_EL1, so the guest can enable single-stepping. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-arm: Correctly handle PSTATE.SS when taking exception to AArch32Peter Maydell2014-08-191-0/+4
| | | | | | | | | | When an exception is taken to AArch32, we must clear the PSTATE.SS bit for the exception handler, and must also ensure that the SS bit is not set in the value saved to SPSR_<mode>. Achieve both of these aims by clearing the bit in uncached_cpsr before saving it to the SPSR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-arm: Adjust debug ID registers per-CPUPeter Maydell2014-08-191-7/+26
| | | | | | | | | | Allow each CPU type to specify the value for the debug ID registers, by putting them in the ARMCPU struct, and use the resulting information to only expose the correct number of watchpoint and breakpoint registers for the CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-arm: Provide both 32 and 64 bit versions of debug registersPeter Maydell2014-08-191-14/+20
| | | | | | | | | Bring the 32 bit and 64 bit views of the debug registers into line by providing the same set of registers in both cases. (This still isn't a complete set, but it is consistent.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14Peter Maydell2014-08-191-3/+8
| | | | | | | | | | | | | Currently the STATE_BOTH shorthand for allowing a single reginfo struct to define handling for both AArch32 and AArch64 views of a register only permits this where the AArch32 view is in cp15. It turns out that the debug registers in cp14 also have neatly lined up encodings; allow these also to share reginfo structs by permitting a STATE_BOTH reginfo to specify the .cp field (and continue to default to 15 if it is not specified). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-arm: Collect up the debug cp register definitionsPeter Maydell2014-08-191-32/+53
| | | | | | | | | | | | | | | At the moment we have a mixed set of mostly dummy register definitions for various debug related registers which have been added piecemeal in order to get Linux kernels to boot. In preparation for actually implementing debug support, bring them all together into one place. This commit doesn't change behaviour: we still expose exactly the same registers and behaviour to the guest in all configurations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-arm: A64: fix TLB flush instructionsAlex Bennée2014-08-041-2/+8
| | | | | | | | | | | | According to the ARM ARM we weren't correctly flushing the TLB entries where bits 63:56 didn't match bit 55 of the virtual address. This exposed a problem when we switched QEMU's internal TARGET_PAGE_BITS to 12 for aarch64. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1406733627-24255-3-git-send-email-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: don't hardcode mask values in arm_cpu_handle_mmu_faultAlex Bennée2014-08-041-2/+2
| | | | | | | | Otherwise we break quickly when we change TARGET_PAGE_SIZE. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1406733627-24255-2-git-send-email-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Fix bit test in sp_el0_accessStefan Weil2014-08-041-1/+1
| | | | | | | | | | Static code analyzers complain about a dubious & operation used for a boolean value. The code does not test the PSTATE_SP bit as it should. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-id: 1406359601-25583-1-git-send-email-sw@weilnetz.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add FAR_EL2 and 3Edgar E. Iglesias2014-08-041-0/+6
| | | | | | | | Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1402994746-8328-7-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add ESR_EL2 and 3Edgar E. Iglesias2014-08-041-0/+8
| | | | | | | | Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1402994746-8328-6-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Make far_el1 an arrayEdgar E. Iglesias2014-08-041-6/+6
| | | | | | | | | | | No functional change. Prepares for future additions of the EL2 and 3 versions of this reg. Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1402994746-8328-5-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Fix new typos (found by codespell)Stefan Weil2014-06-241-1/+1
| | | | | | | | | | | | * accomodate -> accommodate * aquiring -> acquiring * beacuse -> because * loosing -> losing * prefering -> preferring * threshhold -> threshold Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* target-arm: Add ULL suffix to calculation of page sizePeter Maydell2014-06-191-1/+1
| | | | | | | | | | The maximum block size for AArch64 address translation is 2GB. This means that we need a ULL suffix on our shift to avoid shifting into the sign bit of a signed 32 bit integer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1402171881-14343-2-git-send-email-peter.maydell@linaro.org
* target-arm: implement PD0/PD1 bits for TTBCRFabian Aggeler2014-06-191-18/+44
| | | | | | | | | | | | | Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security Extensions). Bits PD0/PD1 are now respected in get_phys_addr_v6/v5() and get_level1_table_address. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Message-id: 1402409556-18574-1-git-send-email-aggelerf@ethz.ch Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Fix errors in writes to generic timer control registersPeter Maydell2014-06-091-3/+3
| | | | | | | | | | | | | | | | | | | | The code for handling writes to the generic timer control registers had several bugs: * ISTATUS (bit 2) is read-only but we forced it to zero on any write * the check for "was IMASK (bit 1) toggled?" incorrectly used '&' where it should be '^' * the handling of IMASK was inverted: we should set the IRQ if ISTATUS is set and IMASK is clear, not if both are set The combination of these bugs meant that when running a Linux guest that uses the generic timers we would fairly quickly end up either forgetting that the timer output should be asserted, or failing to set the IRQ when the timer was unmasked. The result is that the guest never gets any more timer interrupts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401803208-1281-1-git-send-email-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org
* target-arm: A32/T32: Mask CRC value in calling code, not helperPeter Maydell2014-06-091-19/+6
| | | | | | | | | | Bring the 32-bit CRC helper functions into line with the A64 ones, by masking the high bytes of the value in the calling code rather than the helper. This is more efficient since we can determine the mask at translation time. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-7-git-send-email-peter.maydell@linaro.org
* target-arm: Correct handling of UXN bit in ARMv8 LPAE page tablesIan Campbell2014-06-091-9/+8
| | | | | | | | | | | | | | | | | | | | In v8 page tables bit 54 in the PTE is UXN in the EL0/EL1 translation regimes and XN elsewhere. In v7 the bit is always XN. Since we only emulate EL0/EL1 we can just treat this bit as UXN whenever we are in v8 mode. Also correctly extract the upper attributes from the PTE entry, the v8 version tried to avoid extracting the CONTIG bit and ended up with the upper bits being off-by-one. Instead behave the same as v7 and extract (but ignore) the CONTIG bit. This fixes "Bad mode in Synchronous Abort handler detected, code 0x8400000f" seen when modprobing modules under Linux. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Claudio Fontana <claudio.fontana@huawei.com> Cc: Rob Herring <robherring2@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Prepare cpreg writefns/readfns for EL3/SecExtFabian Aggeler2014-06-091-14/+14
| | | | | | | | | | | | This patch changes some readfns/writefns to use raw_write and raw_read functions, which use the fieldoffset specified in ARMCPRegInfo instead of directly accessing the field. This will simplify patches for EL3 & Security Extensions. Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Message-id: 1401962428-14749-1-git-send-email-aggelerf@ethz.ch Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* softmmu: introduce cpu_ldst.hPaolo Bonzini2014-06-051-2/+1
| | | | | | | | | | This will collect all load and store helpers soon. For now it is just a replacement for softmmu_exec.h, which this patch stops including directly, but we also include it where this will be necessary in order to simplify the next patch. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-arm: move arm_*_code to a separate filePaolo Bonzini2014-06-051-0/+1
| | | | | | | These will soon require cpu_ldst.h, so move them out of cpu.h. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-281-1/+1
| | | | | | | | | | Rather than include helper.h with N values of GEN_HELPER, include a secondary file that sets up the macros to include helper.h. This minimizes the files that must be rebuilt when changing the macros for file N. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-arm: A64: Register VBAR_EL3Edgar E. Iglesias2014-05-271-0/+5
| | | | | | | Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-24-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: A64: Register VBAR_EL2Edgar E. Iglesias2014-05-271-0/+21
| | | | | | | Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-23-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Make vbar_write writeback to any CPREGEdgar E. Iglesias2014-05-271-1/+1
| | | | | | | Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-22-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Register EL3 versions of ELR and SPSREdgar E. Iglesias2014-05-271-0/+16
| | | | | | | Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-17-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Register EL2 versions of ELR and SPSREdgar E. Iglesias2014-05-271-0/+16
| | | | | | | Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-16-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add SPSR entries for EL2/HYP and EL3/MONEdgar E. Iglesias2014-05-271-0/+4
| | | | | | | Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-12-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: c12_vbar -> vbar_el[]Edgar E. Iglesias2014-05-271-3/+3
| | | | | | | | | | No functional change. Preparation for adding EL2 and 3 versions of this reg. Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-9-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Make esr_el1 an arrayEdgar E. Iglesias2014-05-271-5/+5
| | | | | | | | | | No functional change. Prepares for future addtion of EL2 and 3 versions of this reg. Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-8-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Make elr_el1 an arrayEdgar E. Iglesias2014-05-271-1/+2
| | | | | | | | | | No functional change. Prepares for future additions of the EL2 and 3 versions of this reg. Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-7-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: implement CPACR register logic for ARMv7Fabian Aggeler2014-05-271-4/+28
| | | | | | | | | | | | | | | | In ARMv7 the CPACR register allows to control access rights to coprocessor 0-13 interfaces. Bits corresponding to unimplemented coprocessors should be RAZ/WI. Bits ASEDIS, D32DIS, TRCDIS are UNK/SBZP if VFP is not implemented and RAO/WI in some cases. Treating TRCDIS as RAZ/WI since we neither implement a trace macrocell nor a CP14 interface to the trace macrocell registers. Since CPACR bits for VFP/Neon access are honoured with the CPACR_FPEN bit in the TB flags, flushing the TLB is not necessary anymore. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Message-id: 1400532968-30668-1-git-send-email-aggelerf@ethz.ch Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm/helper.c: Don't flush the TLB if SCTLR is rewritten unchangedPeter Maydell2014-05-131-0/+7
| | | | | | | | | | | | | | | Linux makes a habit of writing the same value to the SCTLR that it already holds. In a sample boot of the kernel to a shell prompt it wrote the SCTLR with the value it already held 325465 times, and wrote different values just 3 times. Skip flushing the TLB if the SCTLR value isn't actually being changed; this speeds up my sample boot by 3-5%. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1399560029-19007-1-git-send-email-peter.maydell@linaro.org
* target-arm: A64: Fix a typo when declaring TLBI opsEdgar E. Iglesias2014-05-011-12/+12
| | | | | | | | | | Harmless typo as opc1 defaults to zero and opc2 gets re-declared to its correct value. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1398926097-28097-4-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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