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path: root/target-arm/helper.c
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* target-arm: Implement setting guest breakpointsPeter Maydell2014-09-291-2/+124
* target-arm: Make *IS TLB maintenance ops affect all CPUsPeter Maydell2014-09-121-12/+89
* target-arm: Push legacy wildcard TLB ops back into v6Peter Maydell2014-09-121-47/+55
* target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0Peter Maydell2014-09-121-0/+19
* target-arm: Remove comment about MDSCR_EL1 being dummy implementationPeter Maydell2014-09-121-3/+1
* target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32Peter Maydell2014-09-121-0/+26
* target-arm: Implement handling of fired watchpointsPeter Maydell2014-09-121-1/+6
* target-arm: Move extended_addresses_enabled() to internals.hPeter Maydell2014-09-121-11/+0
* target-arm: Implement setting of watchpointsPeter Maydell2014-09-121-3/+132
* target-arm: Implement pmccfiltr_write functionAlistair Francis2014-08-291-0/+9
* target-arm: Remove old code and replace with new functionsAlistair Francis2014-08-291-23/+4
* target-arm: Implement pmccntr_sync functionAlistair Francis2014-08-291-0/+23
* target-arm: Add arm_ccnt_enabled functionAlistair Francis2014-08-291-0/+12
* target-arm: Implement PMCCNTR_EL0 and related registersAlistair Francis2014-08-291-6/+39
* arm: Implement PMCCNTR 32b read-modify-writePeter Crosthwaite2014-08-291-1/+10
* target-arm: Make the ARM PMCCNTR register 64-bitAlistair Francis2014-08-291-10/+9
* target-arm: Implement MDSCR_EL1 as having statePeter Maydell2014-08-191-1/+3
* target-arm: Correctly handle PSTATE.SS when taking exception to AArch32Peter Maydell2014-08-191-0/+4
* target-arm: Adjust debug ID registers per-CPUPeter Maydell2014-08-191-7/+26
* target-arm: Provide both 32 and 64 bit versions of debug registersPeter Maydell2014-08-191-14/+20
* target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14Peter Maydell2014-08-191-3/+8
* target-arm: Collect up the debug cp register definitionsPeter Maydell2014-08-191-32/+53
* target-arm: A64: fix TLB flush instructionsAlex Bennée2014-08-041-2/+8
* target-arm: don't hardcode mask values in arm_cpu_handle_mmu_faultAlex Bennée2014-08-041-2/+2
* target-arm: Fix bit test in sp_el0_accessStefan Weil2014-08-041-1/+1
* target-arm: Add FAR_EL2 and 3Edgar E. Iglesias2014-08-041-0/+6
* target-arm: Add ESR_EL2 and 3Edgar E. Iglesias2014-08-041-0/+8
* target-arm: Make far_el1 an arrayEdgar E. Iglesias2014-08-041-6/+6
* Fix new typos (found by codespell)Stefan Weil2014-06-241-1/+1
* target-arm: Add ULL suffix to calculation of page sizePeter Maydell2014-06-191-1/+1
* target-arm: implement PD0/PD1 bits for TTBCRFabian Aggeler2014-06-191-18/+44
* target-arm: Fix errors in writes to generic timer control registersPeter Maydell2014-06-091-3/+3
* target-arm: A32/T32: Mask CRC value in calling code, not helperPeter Maydell2014-06-091-19/+6
* target-arm: Correct handling of UXN bit in ARMv8 LPAE page tablesIan Campbell2014-06-091-9/+8
* target-arm: Prepare cpreg writefns/readfns for EL3/SecExtFabian Aggeler2014-06-091-14/+14
* softmmu: introduce cpu_ldst.hPaolo Bonzini2014-06-051-2/+1
* target-arm: move arm_*_code to a separate filePaolo Bonzini2014-06-051-0/+1
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-281-1/+1
* target-arm: A64: Register VBAR_EL3Edgar E. Iglesias2014-05-271-0/+5
* target-arm: A64: Register VBAR_EL2Edgar E. Iglesias2014-05-271-0/+21
* target-arm: Make vbar_write writeback to any CPREGEdgar E. Iglesias2014-05-271-1/+1
* target-arm: Register EL3 versions of ELR and SPSREdgar E. Iglesias2014-05-271-0/+16
* target-arm: Register EL2 versions of ELR and SPSREdgar E. Iglesias2014-05-271-0/+16
* target-arm: Add SPSR entries for EL2/HYP and EL3/MONEdgar E. Iglesias2014-05-271-0/+4
* target-arm: c12_vbar -> vbar_el[]Edgar E. Iglesias2014-05-271-3/+3
* target-arm: Make esr_el1 an arrayEdgar E. Iglesias2014-05-271-5/+5
* target-arm: Make elr_el1 an arrayEdgar E. Iglesias2014-05-271-1/+2
* target-arm: implement CPACR register logic for ARMv7Fabian Aggeler2014-05-271-4/+28
* target-arm/helper.c: Don't flush the TLB if SCTLR is rewritten unchangedPeter Maydell2014-05-131-0/+7
* target-arm: A64: Fix a typo when declaring TLBI opsEdgar E. Iglesias2014-05-011-12/+12
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