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path: root/target-arm/helper.c
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* target-arm: Use new revbit functionsRichard Henderson2015-09-151-11/+1
* target-arm: Add VMPIDR_EL2Edgar E. Iglesias2015-09-141-2/+24
* target-arm: Break out mpidr_read_val()Edgar E. Iglesias2015-09-141-1/+6
* target-arm: Add VPIDR_EL2Edgar E. Iglesias2015-09-141-1/+41
* target-arm: Suppress EPD for S2, EL2 and EL3 translationsEdgar E. Iglesias2015-09-141-2/+4
* target-arm: Suppress TBI for S2 translationsEdgar E. Iglesias2015-09-141-1/+3
* target-arm: Add VTTBR_EL2Edgar E. Iglesias2015-09-141-2/+32
* target-arm: Add VTCR_EL2Edgar E. Iglesias2015-09-141-2/+41
* tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt2015-09-111-2/+2
* maint: remove / fix many doubled wordsDaniel P. Berrange2015-09-111-1/+1
* target-arm: Add AArch64 access to PAR_EL1Edgar E. Iglesias2015-09-081-0/+6
* target-arm: Correct opc1 for AT_S12ExxEdgar E. Iglesias2015-09-081-4/+4
* target-arm: Fix AArch32:AArch64 general-purpose register mappingSergey Sorokin2015-09-071-32/+32
* arm: Remove hw_error() usages.Peter Crosthwaite2015-09-071-1/+1
* target-arm: Improve semihosting debug printsChristopher Covington2015-09-071-3/+9
* target-arm: Implement AArch64 TLBI operations on IPAsPeter Maydell2015-08-251-0/+55
* target-arm: Implement missing EL3 TLB invalidate operationsPeter Maydell2015-08-251-0/+76
* target-arm: Implement missing EL2 TLBI operationsPeter Maydell2015-08-251-0/+22
* target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touchPeter Maydell2015-08-251-43/+129
* target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric orderPeter Maydell2015-08-251-8/+8
* target-arm: Implement AArch32 ATS1H* operationsPeter Maydell2015-08-251-0/+22
* target-arm: Enable the AArch32 ATS12NSO opsPeter Maydell2015-08-251-5/+11
* target-arm: Wire up AArch64 EL2 and EL3 address translation opsPeter Maydell2015-08-251-2/+41
* target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translationsPeter Maydell2015-08-251-0/+5
* target-arm: Implement missing ACTLR registersPeter Maydell2015-08-251-6/+15
* target-arm: Implement missing AFSR registersPeter Maydell2015-08-251-0/+24
* target-arm: Implement missing AMAIR registersPeter Maydell2015-08-251-0/+21
* target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registersPeter Maydell2015-08-251-0/+8
* target-arm: Add AArch32 banked register access to secure physical timerPeter Maydell2015-08-131-0/+27
* target-arm: Add the AArch64 view of the Secure physical timerPeter Maydell2015-08-131-0/+87
* target-arm: Add debug check for mismatched cpreg resetsPeter Maydell2015-08-131-1/+1
* target-arm: Add the Hypervisor timerEdgar E. Iglesias2015-08-131-0/+68
* target-arm: Pass timeridx as argument to various timer functionsEdgar E. Iglesias2015-08-131-22/+77
* target-arm: Rename and move gt_cnt_resetEdgar E. Iglesias2015-08-131-7/+5
* target-arm: Add CNTHCTL_EL2Edgar E. Iglesias2015-08-131-2/+31
* target-arm: Add CNTVOFF_EL2Edgar E. Iglesias2015-08-131-6/+41
* target-arm: Fix broken SCTLR_EL3 resetPeter Maydell2015-07-151-0/+1
* target-arm: fix write helper for TLBI ALLE1ISSergey Fedorov2015-07-061-1/+1
* semihosting: create SemihostingConfig structure and semihost.hLeon Alrae2015-06-191-3/+4
* target-arm: Implement PMSAv7 MPUPeter Crosthwaite2015-06-191-1/+173
* target-arm: Add registers for PMSAv7Peter Crosthwaite2015-06-191-7/+83
* target-arm/helper.c: define MPUIR registerPeter Crosthwaite2015-06-191-0/+10
* target-arm: Do not reset sysregs marked as ALIASSergey Fedorov2015-06-191-19/+9
* arm: helper: rename get_phys_addr_mpuPeter Crosthwaite2015-06-151-5/+5
* arm: Implement uniprocessor with MP configPeter Crosthwaite2015-06-151-2/+4
* arm: Refactor get_phys_addr FSR return mechanismPeter Crosthwaite2015-06-151-58/+70
* arm: helper: Factor out CP regs common to [pv]msaPeter Crosthwaite2015-06-151-9/+14
* arm: Don't add v7mp registers in MPU systemsPeter Crosthwaite2015-06-151-1/+2
* arm: Do not define TLBTR in PMSA systemsPeter Crosthwaite2015-06-151-3/+10
* target-arm: Use the kernel's idea of MPIDR if we're using KVMPavel Fedin2015-06-151-6/+3
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