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path: root/target-arm/helper.c
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* target-arm: Add support for S1 + S2 MMU translationsEdgar E. Iglesias2015-10-271-7/+31
* target-arm: Add S2 translation to 32bit S1 PTWsEdgar E. Iglesias2015-10-271-5/+17
* target-arm: Add S2 translation to 64bit S1 PTWsEdgar E. Iglesias2015-10-271-2/+48
* target-arm: Add ARMMMUFaultInfoEdgar E. Iglesias2015-10-271-12/+20
* target-arm: Avoid inline for get_phys_addrEdgar E. Iglesias2015-10-271-8/+8
* target-arm: Add support for S2 page-table protection bitsEdgar E. Iglesias2015-10-271-4/+37
* target-arm: Add computation of starting level for S2 PTWEdgar E. Iglesias2015-10-271-13/+101
* target-arm: lpae: Rename granule_sz to strideEdgar E. Iglesias2015-10-271-15/+15
* target-arm: lpae: Replace tsz with computed inputsizeEdgar E. Iglesias2015-10-271-11/+11
* target-arm: Add support for AArch32 S2 negative t0szEdgar E. Iglesias2015-10-271-1/+17
* target-arm: lpae: Move declaration of t0sz and t1szEdgar E. Iglesias2015-10-271-2/+3
* target-arm: lpae: Make t0sz and t1sz signed integersEdgar E. Iglesias2015-10-271-2/+2
* target-arm: Add HPFAR_EL2Edgar E. Iglesias2015-10-271-0/+12
* target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ)Soren Brinkmann2015-10-271-0/+16
* target-arm: Add MDCR_EL2Sergey Fedorov2015-10-161-0/+12
* target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregsDavorin Mista2015-10-161-2/+23
* target-arm: Avoid calling arm_el_is_aa64() function for unimplemented ELSergey Sorokin2015-10-161-2/+13
* target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin2015-10-161-1/+5
* target-arm: Add missing 'static' attributeStefan Weil2015-10-161-1/+1
* arm: clarify the use of muldiv64()Laurent Vivier2015-09-251-6/+8
* target-arm: Use new revbit functionsRichard Henderson2015-09-151-11/+1
* target-arm: Add VMPIDR_EL2Edgar E. Iglesias2015-09-141-2/+24
* target-arm: Break out mpidr_read_val()Edgar E. Iglesias2015-09-141-1/+6
* target-arm: Add VPIDR_EL2Edgar E. Iglesias2015-09-141-1/+41
* target-arm: Suppress EPD for S2, EL2 and EL3 translationsEdgar E. Iglesias2015-09-141-2/+4
* target-arm: Suppress TBI for S2 translationsEdgar E. Iglesias2015-09-141-1/+3
* target-arm: Add VTTBR_EL2Edgar E. Iglesias2015-09-141-2/+32
* target-arm: Add VTCR_EL2Edgar E. Iglesias2015-09-141-2/+41
* tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt2015-09-111-2/+2
* maint: remove / fix many doubled wordsDaniel P. Berrange2015-09-111-1/+1
* target-arm: Add AArch64 access to PAR_EL1Edgar E. Iglesias2015-09-081-0/+6
* target-arm: Correct opc1 for AT_S12ExxEdgar E. Iglesias2015-09-081-4/+4
* target-arm: Fix AArch32:AArch64 general-purpose register mappingSergey Sorokin2015-09-071-32/+32
* arm: Remove hw_error() usages.Peter Crosthwaite2015-09-071-1/+1
* target-arm: Improve semihosting debug printsChristopher Covington2015-09-071-3/+9
* target-arm: Implement AArch64 TLBI operations on IPAsPeter Maydell2015-08-251-0/+55
* target-arm: Implement missing EL3 TLB invalidate operationsPeter Maydell2015-08-251-0/+76
* target-arm: Implement missing EL2 TLBI operationsPeter Maydell2015-08-251-0/+22
* target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touchPeter Maydell2015-08-251-43/+129
* target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric orderPeter Maydell2015-08-251-8/+8
* target-arm: Implement AArch32 ATS1H* operationsPeter Maydell2015-08-251-0/+22
* target-arm: Enable the AArch32 ATS12NSO opsPeter Maydell2015-08-251-5/+11
* target-arm: Wire up AArch64 EL2 and EL3 address translation opsPeter Maydell2015-08-251-2/+41
* target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translationsPeter Maydell2015-08-251-0/+5
* target-arm: Implement missing ACTLR registersPeter Maydell2015-08-251-6/+15
* target-arm: Implement missing AFSR registersPeter Maydell2015-08-251-0/+24
* target-arm: Implement missing AMAIR registersPeter Maydell2015-08-251-0/+21
* target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registersPeter Maydell2015-08-251-0/+8
* target-arm: Add AArch32 banked register access to secure physical timerPeter Maydell2015-08-131-0/+27
* target-arm: Add the AArch64 view of the Secure physical timerPeter Maydell2015-08-131-0/+87
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