summaryrefslogtreecommitdiffstats
path: root/target-arm/helper.c
Commit message (Expand)AuthorAgeFilesLines
* target-arm: Add ARM_CP_IO notation to PMCR reginfoPeter Maydell2014-03-171-0/+1
* misc: Fix typos in commentsStefan Weil2014-03-151-1/+1
* cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber2014-03-131-1/+1
* cputlb: Change tlb_flush() argument to CPUStateAndreas Färber2014-03-131-10/+29
* cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber2014-03-131-4/+10
* exec: Change cpu_abort() argument to CPUStateAndreas Färber2014-03-131-10/+25
* cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-14/+11
* cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber2014-03-131-4/+9
* cpu: Factor out cpu_generic_init()Andreas Färber2014-03-131-13/+1
* target-arm: Clean up ENV_GET_CPU() usageAndreas Färber2014-03-131-5/+7
* target-arm: Implements the ARM PMCCNTR registerAlistair Francis2014-03-101-4/+85
* target-arm: Fix incorrect setting of E bit in CPSRPeter Maydell2014-03-101-1/+1
* target-arm: Add support for AArch32 ARMv8 CRC32 instructionsWill Newton2014-02-261-0/+39
* target-arm: Implement AArch64 view of CPACRPeter Maydell2014-02-261-1/+2
* target-arm: Store AIF bits in env->pstate for AArch32Peter Maydell2014-02-261-12/+17
* target-arm: Implement AArch64 OSLAR_EL1 sysreg as WIPeter Maydell2014-02-261-0/+4
* target-arm: Implement AArch64 dummy breakpoint and watchpoint registersPeter Maydell2014-02-261-0/+32
* target-arm: Implement AArch64 ID and feature registersPeter Maydell2014-02-261-0/+45
* target-arm: Implement AArch64 generic timersPeter Maydell2014-02-261-11/+72
* target-arm: Implement AArch64 MPIDRPeter Maydell2014-02-261-2/+4
* target-arm: Implement AArch64 TTBR*Peter Maydell2014-02-261-59/+30
* target-arm: Implement AArch64 VBAR_EL1Peter Maydell2014-02-261-1/+8
* target-arm: Implement AArch64 TCR_EL1Peter Maydell2014-02-261-3/+16
* target-arm: Implement AArch64 SCTLR_EL1Peter Maydell2014-02-261-1/+2
* target-arm: Implement AArch64 memory attribute registersPeter Maydell2014-02-261-1/+23
* target-arm: Implement AArch64 dummy MDSCR_EL1Peter Maydell2014-02-261-0/+6
* target-arm: Implement AArch64 TLB invalidate opsPeter Maydell2014-02-261-0/+73
* target-arm: Implement AArch64 cache invalidate/clean opsPeter Maydell2014-02-261-0/+47
* target-arm: Implement AArch64 MIDR_EL1Peter Maydell2014-02-261-0/+3
* target-arm: Implement AArch64 CurrentEL sysregPeter Maydell2014-02-261-0/+3
* target-arm: A64: Make cache ID registers visible to AArch64Peter Maydell2014-02-261-10/+21
* target-arm: Fix raw read and write functions on AArch64 registersPeter Maydell2014-02-261-2/+6
* target-arm: Load correct access bits from ARMv5 level 2 page table descriptorsPeter Maydell2014-02-261-1/+1
* target-arm: Fix incorrect arithmetic constructing short-form PAR for ATS opsPeter Maydell2014-02-261-2/+2
* target-arm: Fix incorrect type for value argument to write_raw_cp_regPeter Maydell2014-02-201-1/+1
* target-arm: Remove failure status return from read/write_raw_cp_regPeter Maydell2014-02-201-24/+12
* target-arm: Drop success/fail return from cpreg read and write functionsPeter Maydell2014-02-201-173/+115
* target-arm: Convert miscellaneous reginfo structs to accessfnPeter Maydell2014-02-201-25/+19
* target-arm: Convert generic timer reginfo to accessfnPeter Maydell2014-02-201-56/+66
* target-arm: Convert performance monitor reginfo to accessfnPeter Maydell2014-02-201-42/+28
* target-arm: Stop underdecoding ARM946 PRBS registersPeter Maydell2014-02-201-23/+24
* target-arm: Restrict check_ap() use of S and R bits to v6 and earlierPeter Maydell2014-02-201-0/+3
* target-arm: Define names for SCTLR bitsPeter Maydell2014-02-201-8/+8
* exec: Make stl_*_phys input an AddressSpaceEdgar E. Iglesias2014-02-111-1/+2
* exec: Make ldq/ldub_*_phys input an AddressSpaceEdgar E. Iglesias2014-02-111-1/+2
* exec: Make ldl_*_phys input an AddressSpaceEdgar E. Iglesias2014-02-111-6/+9
* target-arm: Add set_neon_rmode helperWill Newton2014-01-311-0/+17
* target-arm: Move arm_rmode_to_sf to a shared location.Will Newton2014-01-311-0/+28
* target-arm: A64: Add support for FCVT between half, single and doublePeter Maydell2014-01-081-0/+20
* target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructionsPeter Maydell2014-01-081-0/+45
OpenPOWER on IntegriCloud